interface DAC in VHDL

dpt30 said:

Hi,
I´m trying to interface a DAC converter in VHDL,in order to send a pulse, but i´m new in this type of design language.
so i need some help. I´m interested in the vhdl code if it would be possible. Thank you very much.

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dpt30 said:

Hi,
I´m trying to interface a DAC converter in VHDL,in order to send a pulse, but i´m new in this type of design language.
so i need some help. I´m interested in the vhdl code if it would be possible. Thank you very much.

Click to expand...

cvc said:

dpt30 said:

Hi,
I´m trying to interface a DAC converter in VHDL,in order to send a pulse, but i´m new in this type of design language.
so i need some help. I´m interested in the vhdl code if it would be possible. Thank you very much.

Click to expand...

Yes, we have done SAR (Successive Approx) like DAC in VHDL @ www.cvcblr.com Output ports can be real too!

Are you doing for modeling alone or for FPGA/ASIC?

TeamCVC
www.cvcblr.com/blog

Click to expand...