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Interface between c# GUI and FPGA

Qamar Shafi

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I'm new to FPGA i'm a undergraduate student i'm into my final year project where i have to interface my GUI with the FPGA or please just tell me how to i use my Gui which is made in c sharp using visual studio how i can program GUI that i can transmit anything and should able to recieve it on FPGA
 

KlausST

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Hi,

You need to provide useful informations.
Not clear:
* what your GUI is (OS, functions...)
* what your FPGA is (type, function...)
* what you want to control
* what interface is between GUI and FPFA (data rate, protocol ...)

In any case: draw a sketch with good description. Show examples of what you want to achieve...
The more detailed the better

Klaus
 

FlyingDutch

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Hello,

if you are using "Windows Forms" application (C# .NET on Windows OS) - then you can use class "SerialPort" from "System.IO.Ports". You can program the virtual serial port using this class (on PC computer). On the FPGA board you have to use such konverter (USB-UART):


Then you also have to implement UART on your FPGA project. Then one side of converter you are attaching to UART pins (implemented on FPGA chip) and the second side -> usb socket you are connecting to your PC computer. This is likely that you have to also use logic level converters (low voltage on FPGA side). Then you be able to transmit data between PC box and FPGA board. Some FPGA boards has hardware UART implemented - then you can just use it.

See this link:

https://www.codeproject.com/Articles/678025/Serial-Comms-in-Csharp-for-Beginners

it should be helpful for C# serial port programming (PC box).

Regards
 

Qamar Shafi

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yes i have coded in c# but how to ensure coding on FPGA how FPGA will understand what is coming from pc
 

TrickyDicky

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You need to write the logic that interprets the incoming commands + data and does something with them.
 

Qamar Shafi

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where i have to write logic in verilog??
 

FlyingDutch

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where i have to write logic in verilog??
Hello,

you didn't write what is purpose of your desing in FPGA. You also didn't attached any code in HDL of your project - even skeleton. We are not fortune-tellers. Maybe describe what tasks your project have to pursue, then someone will be able to give you hints.

Regards
 

Qamar Shafi

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how to make LED's of the FPGA blink by using a GUI built in C sharp windows forms
yes i have to add serial port in GUI
but what i write in that GUI and then how to code in verilog for FPGA so that lights should blink
if u want me to read something to do this plzz tell me the website where i can study this and able to interface between FPGA and PC
 

KlausST

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Hi,

You don't show a drawing.
You don't answer our questions. (It seems you did not even read them)
We see no effort on your own.
Thus we don't know what you need.

We want to help, but you make it impossible.

*******
I can only recommend:
There are many circuits, reference circuits, developmemt boards with schematics in the internet.
Every FPGA development board offer an interface to a PC....
Look through some of them, find out which one suits you most.
Give us the link to it.
Tell us what you want to modify and why.
Search the internet for solutions.
Ask elaborated questions.

A "half line post" surely is not enough information. And not a 1 line, and not a 4 line....

Klaus
 

KlausST

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Hi,

Didn't you read post#2?
On a sheet of paper...with or without colors...computer drawn ...it does not matter.

We just need to understand your situation and your problem.

****
Honestly: We write lenghty posts, try to explain, ask for informations, try to help. But we see no effort from your side.
If you are not willing to provide useful informations or a drawing, no internet link.. show what you have done so far ...
... then don't expect that I (we?) spend more time on this thread.

Klaus
 

Qamar Shafi

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Let me tell you actually my project is to Design and Implementation of Test Controller (ASIC) for X Band Quad Transmit Receive Module
but for that i have to make a gui so that i can send commands via FPGA but first thing is to interface the computer and FPGA for that my advisor gave me a task to learn how to interface both and just blink Artix-7 LED's from GUI.My GUI is looks like1596783824852.png
 

Qamar Shafi

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now tell me how to send commands to FpGA and how that will respond by using it
FPGA is Artix-7
communication protocol is via UART
 

TrickyDicky

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You need to write an FPGA design that receives commands (defined by you), decodes the commands and turns on/off the LEDs. You will also need code for a UART controller.
There are many UART examples out there....
 

Qamar Shafi

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that i know but how to do it i'm asking that
 

KlausST

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Hi,

my last attempt... (hopefully others are willing to help you)
UART is no protocol. UART is a PART of an interface.
--> So I must assume you even didn´t do an internet search "What is an UART".
--> you have to do so simple internet searches on your own!

A UART can be implemented in an FPGA. Over one million hits for an internet search "How to implement UART on a FPGA".
Documents, libraries, descriptions, examples, even videos. What more do you need?
Are you too lazy to go through ten (or so) of the first hits? - At least you didn´t tell, although I asked for it..
Why don´t you tell us which of them you´ve read, what is clear and what is not clear...

It seems we need to ask for each item several times .. you just look for someone to do your job.
I like to support people who try to find a solution on their own, who show their effort, show how hard they work.

I don´t see this here, thus I leave the thread.
The same time I honestly hope that you can convince other people that you work hard and thus motivate them to help you. Good luck
 

dpaul

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that i know but how to do it i'm asking that
Ok, given that you are new in this field, your best approach would be to split up the "todo"s.
You decide for yourself, which part you want to start with.
As others have pointed out, there is a design implementation part on FPGA (Verilog/VHDL) and command interfacing part using GUI. In my option it is better to start with the design impl part. How to pass the commands from GUI can be the next task. So plan accordingly.

GUI --> Serial ctrl i/f (TeraTerm/Putty) --> UART data tx to FPGA --> Save data to registers --> Read register values to blink LEDs

This is what I can imagine as a flow. Now it is your task to come up with ideas as to how to implement the above stages.
 
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ads-ee

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Now it is your task to come up with ideas as to how to implement the above stages.
What if they don't know anything about logic design and hardware?

From what I've read in this thread, I don't think they have any background in digital design, they appear to only know software. I think they first need to go through all the simple tutorials on using FPGAs (and do some studying on logic design) before tackling this assignment.

If you type "FPGA tutorial" in a google search and you will find there are many resources on the subject.
 

MarkPh

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I'm new to FPGA i'm a undergraduate student i'm into my final year project where i have to interface my GUI with the FPGA or please just tell me how to i use my Gui which is made in c sharp using visual studio how i can program GUI that i can transmit anything and should able to recieve it on FPGA
If you want to do it very fast you can use Instant SoC.
You simply write a few lines of C++ code and the tool generates the VHDL code.
There are ready UART classes etc.
Here you can see an example using UART.
 

FlyingDutch

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If you want to do it very fast you can use Instant SoC.
You simply write a few lines of C++ code and the tool generates the VHDL code.
There are ready UART classes etc.
Here you can see an example using UART.
Hello,
I think that such solution might be not accepted by the teacher (I think it should be project in pure HDL language).

I suggest Qamar start from implementing simple UART on FPGA and test it on FPGA board - using for example similiar USB-Serial converter I mentioned in my first post. For first tests 'Putty" application can be used. We should know on which FPGA chip this project will be implemented because the choice off software tool for synthessis dependes. There are many open-source implementation of UART on Opencores.org website:
https://opencores.org/projects?expanded=Coprocessor,Communication controller

Unfortunately most of them are implemented in VHDL (Qmar said that it should be Verilog).

There is one very simple implementation in Verilog (without hardware FIFO):

https://opencores.org/projects/mmuart

This is simplest implementation it can be - only two files in Verilog (uart.v and uart_transceiver.v):

Code:
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program.  If not, see <http://www.gnu.org/licenses/>.
*/

module uart #(
    parameter csr_addr = 4'h0,
    parameter clk_freq = 100000000,
    parameter baud = 115200
) (
    input sys_clk,
    input sys_rst,
   
    input [13:0] csr_a,
    input csr_we,
    input [31:0] csr_di,
    output reg [31:0] csr_do,

    output rx_irq,
    output tx_irq,

    input uart_rx,
    output uart_tx
);

reg [15:0] divisor;
wire [7:0] rx_data;
wire [7:0] tx_data;
wire tx_wr;

reg thru;
wire uart_tx_transceiver;

uart_transceiver transceiver(
    .sys_clk(sys_clk),
    .sys_rst(sys_rst),

    .uart_rx(uart_rx),
    .uart_tx(uart_tx_transceiver),

    .divisor(divisor),

    .rx_data(rx_data),
    .rx_done(rx_irq),

    .tx_data(tx_data),
    .tx_wr(tx_wr),
    .tx_done(tx_irq)
);

assign uart_tx = thru ? uart_rx : uart_tx_transceiver;

/* CSR interface */
wire csr_selected = csr_a[13:10] == csr_addr;

assign tx_data = csr_di[7:0];
assign tx_wr = csr_selected & csr_we & (csr_a[1:0] == 2'b00);

parameter default_divisor = clk_freq/baud/16;

always @(posedge sys_clk) begin
    if(sys_rst) begin
        divisor <= default_divisor;
        csr_do <= 32'd0;
    end else begin
        csr_do <= 32'd0;
        if(csr_selected) begin
            case(csr_a[1:0])
                2'b00: csr_do <= rx_data;
                2'b01: csr_do <= divisor;
                2'b10: csr_do <= thru;
            endcase
            if(csr_we) begin
                case(csr_a[1:0])
                    2'b00:; /* handled by transceiver */
                    2'b01: divisor <= csr_di[15:0];
                    2'b10: thru <= csr_di[0];
                endcase
            end
        end
    end
end

endmodule
Code:
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
* Copyright (C) 2007 Das Labor
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program.  If not, see <http://www.gnu.org/licenses/>.
*/

module uart_transceiver(
    input sys_rst,
    input sys_clk,

    input uart_rx,
    output reg uart_tx,

    input [15:0] divisor,

    output reg [7:0] rx_data,
    output reg rx_done,

    input [7:0] tx_data,
    input tx_wr,
    output reg tx_done
);

//-----------------------------------------------------------------
// enable16 generator
//-----------------------------------------------------------------
reg [15:0] enable16_counter;

wire enable16;
assign enable16 = (enable16_counter == 16'd0);

always @(posedge sys_clk) begin
    if(sys_rst)
        enable16_counter <= divisor - 16'b1;
    else begin
        enable16_counter <= enable16_counter - 16'd1;
        if(enable16)
            enable16_counter <= divisor - 16'b1;
    end
end

//-----------------------------------------------------------------
// Synchronize uart_rx
//-----------------------------------------------------------------
reg uart_rx1;
reg uart_rx2;

always @(posedge sys_clk) begin
    uart_rx1 <= uart_rx;
    uart_rx2 <= uart_rx1;
end

//-----------------------------------------------------------------
// UART RX Logic
//-----------------------------------------------------------------
reg rx_busy;
reg [3:0] rx_count16;
reg [3:0] rx_bitcount;
reg [7:0] rx_reg;

always @(posedge sys_clk) begin
    if(sys_rst) begin
        rx_done <= 1'b0;
        rx_busy <= 1'b0;
        rx_count16  <= 4'd0;
        rx_bitcount <= 4'd0;
    end else begin
        rx_done <= 1'b0;

        if(enable16) begin
            if(~rx_busy) begin // look for start bit
                if(~uart_rx2) begin // start bit found
                    rx_busy <= 1'b1;
                    rx_count16 <= 4'd7;
                    rx_bitcount <= 4'd0;
                end
            end else begin
                rx_count16 <= rx_count16 + 4'd1;

                if(rx_count16 == 4'd0) begin // sample
                    rx_bitcount <= rx_bitcount + 4'd1;

                    if(rx_bitcount == 4'd0) begin // verify startbit
                        if(uart_rx2)
                            rx_busy <= 1'b0;
                    end else if(rx_bitcount == 4'd9) begin
                        rx_busy <= 1'b0;
                        if(uart_rx2) begin // stop bit ok
                            rx_data <= rx_reg;
                            rx_done <= 1'b1;
                        end // ignore RX error
                    end else
                        rx_reg <= {uart_rx2, rx_reg[7:1]};
                end
            end
        end
    end
end

//-----------------------------------------------------------------
// UART TX Logic
//-----------------------------------------------------------------
reg tx_busy;
reg [3:0] tx_bitcount;
reg [3:0] tx_count16;
reg [7:0] tx_reg;

always @(posedge sys_clk) begin
    if(sys_rst) begin
        tx_done <= 1'b0;
        tx_busy <= 1'b0;
        uart_tx <= 1'b1;
    end else begin
        tx_done <= 1'b0;
        if(tx_wr) begin
            tx_reg <= tx_data;
            tx_bitcount <= 4'd0;
            tx_count16 <= 4'd1;
            tx_busy <= 1'b1;
            uart_tx <= 1'b0;
`ifdef SIMULATION
            $display("UART: %c", tx_data);
`endif
        end else if(enable16 && tx_busy) begin
            tx_count16  <= tx_count16 + 4'd1;

            if(tx_count16 == 4'd0) begin
                tx_bitcount <= tx_bitcount + 4'd1;
               
                if(tx_bitcount == 4'd8) begin
                    uart_tx <= 1'b1;
                end else if(tx_bitcount == 4'd9) begin
                    uart_tx <= 1'b1;
                    tx_busy <= 1'b0;
                    tx_done <= 1'b1;
                end else begin
                    uart_tx <= tx_reg[0];
                    tx_reg <= {1'b0, tx_reg[7:1]};
                end
            end
        end
    end
end

endmodule
You said something about Artix-7 FPGA - in such case the software tool for synthessis it will be Xilinx Vivado. Just try to install free Vivado Webpack on your computer and try to implement this UART project. If you have it working (UART) we can talk about next steps to finish your project.

Regards
 
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