Interesting Digital Design question

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s0shinde

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Design a logic which mimics a infinite width register. It takes input serially 1 bit at a time. Output is asserted high when this register holds a value which is divisible by 5.

For example:

Input Sequence Value Output
1 1 1 0
0 10 2 0
1 101 5 1
0 1010 10 1
1 10101 21 0


(Use a FSM to create this)

Any solution to this?????
 

Can anyone confirm if the answer I attached is correct? The diagram does not look that good?
 

shinde do we need to take the register length as 4? if yes, then why hav u taken the state S5? and why did u send the condition 0/0 from S2 to S1. i think it should go fro S2 to S2 till it gets 1/0 condition.
do correct me if im wrong.

Added after 1 hours 9 minutes:

if u say that register size is of 4bits then here is what i feel the FSM should be.
 

hello haneet,
What will happen if we give an input 1001 to your statemachine? Don't you think your statemachine will detect that as divisible by 5??? Correct me if I am wrong!

Thanks and Regards.
 

s0shinde said:
Can anyone confirm if the answer I attached is correct? The diagram does not look that good?
Click to expand...

Hi Shinde,

Could you please explain more on your state diagram ? Did you construct it with remainders ?
 

KaptainBug, this was last posted on 17th December 2006, 10:00. I doubt s0shinde even uses these forums anymore.
 

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