Interconnect the wires of particular nodes of schematic in array in cadence virtuoso

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parminder

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HI, i want to interconnect the particular wire of instance in an array automatically, is there any way that while copying instance in row, it gets connected automatically or i need to interconnect the wires manually ? ( cadence virtuoso IC6)

in the attachment A,A bar node of all 4 instances must be connected to , while B node is not connected to each other.
 

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You can use named nets and an iterated instance to do
this efficiently. Each "pin" (consider it a pin-stack) has an
ordered list. So, like, a ripple counter could have one
iterated DFF instance, the D pin (stack) might have
<Dprime,Q<0:6> while the output rank is Q<0:7> and
the CK pin is a single shorting wire to the clock source.
Much better than a wireball, as long as you keep the
bookkeeping straight.

Probing that can be a bitch, though, so I usually will take
those bundled nets out to singlets with a trivial load element
that lets me plot-by-pick, somewhere that doesn't mess
with core schematic prettiness.
 

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so basically you mean to say that i simply connect "A" wire to my voltage source(acc. to my circuit design) and label B wire as B <0:3> ?
 

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Kindasortanotexactly.

You need to understand the label form of busses that comprise
non-homogeneous fields (like, input D might be [A,B<0:2>]
while Q is a homogeneous B<0:3> - and my special char
syntax is for illustration only), and the instances must be
named consistently with the net assignments (like the DFFs
may be I7<0:3>) so every pin in the instance-bundle has a
bundle-net to satisfy it and vice versa.
 
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