Interconnect Cap Verification of Cadence Layout with CST MWS

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emreamrzohny

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Does anyone know how to import a Cadence GDSII/dxf file into CST Microwave Studio to perform a verification of the interconnect capacitance.

I don't trust the results of Assura and I would like to verify the results with a 3D EM simulator.

Should I draw everything again by hand or is there a way to directly import the extracted design ? ( If not CST MWS then Momentum or Sonnet ? )
 


Re: Interconnect Cap Verification of Cadence Layout with CST

Manjunatha_hv said:
Even it directly interfaces to Cadence Virtuoso...
Click to expand...

Here's a description of the design flow for Sonnet within the Cadence RFIC environment:

**broken link removed**

See page 15 ff for a design flow overview with some screenshots.

For interconnect/lines, you might want to use the RLCG model (called "mtline" in Spectre). On page 43 ff, there is a description hot to get create that output data.
 

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