Intellectual Property blocks .... are 3rd party sources being marginalized?

[beingbobbyorr]

Assuming a fair number of you read John Cooley's DeepChip . . . .


Gary Smith's study on IP Reuse in SoC designs
DeepChip.com

Biotronik's case study of IP reuse
DeepChip.com

A discussion of the real life drama of IP reuse
DeepChip.com


. . . . . I was stunned to hear Gary Smith's claim that ASIC houses get only 7% of their IP from 3rd-party shops (the balance coming from Synopsys & in-house).

I'd think that IP diversification would be an important strategic goal .... for the same reason we seek it in H/W component suppliers, EDA tool vendors, our personal investment portfolios, etc.,

Can those of you who work on ASIC teams confirm or deny that heavy emphasis on "Synopsys & in-house" IP, at the expense of blocks from 3rd-party 'Mom-n-Pop' sources? Explanations as to why you go one way or the other are also appreciated.

 

[rca]

1- what do you include in IP?, std-cell/memories/pad & RTL code (like I2C/USB/ARM....)
2- I beleived most of the designer used external libraries (std cell/memories/pad)
3- In our design center we mainly used external core like ARM, or bought instruction set ro rebuild the core, to have something patented and "protected" from patent attacks. There are some many patents, it is not so easy to build a new open programming processor/dsp.
4- for small modules like spi/uart/dma/pcm/i2c..., we used custom made.

 

[beingbobbyorr]

1- what do you include in IP?, std-cell/memories/pad & RTL code (like I2C/USB/ARM....)

Because I'm FPGA-centric, I was thinking
-- source code IP
-- encrypted source code IP
-- soft IP (netlist + simulation model that is not the synthesizable code). In FPGA-land "netlist" might be a Xilinx *.ngc file (Altera, Lattice, etc., have equivalents) and not EDIF.

I hadn't thought about hard IP (netlist + physcial layout), because again, being FPGA-centric, all our "hard IP" is built into the silicon, but I can imagine ASICs use a lot more of that.

2- I beleived most of the designer used external libraries (std cell/memories/pad)

Does external = Foundary IP or 3rd-party?

4- for small modules like spi/uart/dma/pcm/i2c..., we used custom made.

Does custom = in-house (i.e., you) or 3rd-party?

 

[wsong0210]

you should clarify you are talking about FPGA at the first place.
There is actually rarely, if not non-existed, to use a soft-IP in ASIC chip.
ASIC designer may have some encrypted codes from IP vendors (foundry or 3rd party), but they are usually for simulation.
In other words, IPs in ASIC are hard IPs in most of the cases and the behavioural equivalent simulation models for the hard IP may provide in encrypted verilog if they dont what customers to know.

For FPGA, it is kind impossible to use a 3rd party hard IP as the hard wiring will easily cause P&R failures in your implementation process, no matter Xilinx or Altera.
Therefore most of the time, customers are provide with soft IPs which can be placed like normal designs.

It is very rare to see a source IP, unless most of it is actually hard IPs. Such as the memory or DCM you can get from Xilinx.

For the ASIC world,
Currently I believe people are more willing to use the IP provide inside their own company, like ST engineers are more willing to use IPs provided by other ST departments.
Using IPs from 3rd party is not reliable sometime as it may be difficult to use it, the IP may not be fully tested. It will be a big failure if the tape-out fails because of an IP error.
However, engineers are willing to use foundry IPs or 3rd part memory IPs are they have been fully tested and proved usable by many companies.

 

[rberek]

Using your own IP allows you to have 100% control.

* You have the source files and the simulation envoronment. You do not have to wait for the vendor or a 3rd party to make the changes you want on their own timeline, if they want to make the changes at all.

* You can put the IP in as many designs as you want, and you can sell as much of each design as you want. Many licensing agreements put limits on how often you can use the core, and many want royalties for each unit of each design containing their core.

* You do not have to worry about the IP vendor making changes in their licensing agreements when they want to do so.

* You do not have to worry about the "Mom and Pop" vendor going out of business, or perhaps worse, being bought by a competitor.

* You do not have to worry about Mom and Pop Inc violating a patent, getting sued and you now have to pay royalties to the Patent Trolls

Large companies have the staff and experience and money to rely on their own IP almost exclusively, and many do, only using external IP when they absolutely have to. Medium and small companies are often not in the same position, so their choices are different.

r.b.