Aug 30, 2011 #1 R reza.ghanaatian Newbie level 1 Joined Aug 30, 2011 Messages 1 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,292 Hi, I want to instantiate a module 16 time and it is so boring. Is there a way that I can use a "for loop" and only one istantiation? I used these syntax and ModelSim doed not accept it. I should say that I need my code to be synthesizable also.
Hi, I want to instantiate a module 16 time and it is so boring. Is there a way that I can use a "for loop" and only one istantiation? I used these syntax and ModelSim doed not accept it. I should say that I need my code to be synthesizable also.
Aug 30, 2011 #2 FvM Super Moderator Staff member Joined Jan 22, 2008 Messages 52,420 Helped 14,749 Reputation 29,780 Reaction score 14,101 Trophy points 1,393 Location Bochum, Germany Activity points 298,099 Seems like you lacking a good Verilog text book or tutorial. Read about the generate loop statement.
Sep 2, 2011 #3 L ljxpjpjljx Advanced Member level 3 Joined May 5, 2008 Messages 968 Helped 80 Reputation 162 Reaction score 56 Trophy points 1,308 Location Shang Hai Activity points 4,679 you can use "generate" method to do so!