Instantiating multiple subcircuits [VHDL]

[eafox]

Is it possible to instantiate multiple subcircuits using a loop?
I'm thinking about something like this:

...
generic( N: integer:= 4);
...
for i in 1 to N loop
    unit_i: entity work.subcircuit(arch)
        port map(...)
end loop;
...

Thanks,

Edson

 

[eafox]

I found a solution. There is a special loop for subcircuit instantiation. This loop doesn't requiere to be inside a process.

generic(N: integer:= 4);
...
ssgen: for i in 1 to N generate
    unit: entity work.subcircuit(arch)
        port map(...);
end generate ssgen;