ranayehya
Junior Member level 3
Hello!
I am new in verilog and I begin working on I2C protocol hardware implementation
The master code works well
but when I combine all files together the master code does not work as it was
"sda_reg" is the problem and I do not know what I did wrong
the top code
And "sda" is inout
This is the piece of code related to "sda" (from master code)
I am new in verilog and I begin working on I2C protocol hardware implementation
The master code works well
but when I combine all files together the master code does not work as it was
"sda_reg" is the problem and I do not know what I did wrong
the top code
Code:
module top;
wire clock,reset,start;
wire [7:0]addr;
wire [7:0]data;
wire [7:0] out;
wire scl_w ,sda_w ;
master m1(.clk(clock),.start(start),.reset(reset),.addr(addr),.data(data),.scl(scl_w),.sda(sda_w));
slave s1(.scl(scl_w),.sda(sda_w),.data(out));
endmoduleThis is the piece of code related to "sda" (from master code)
Code:
assign sda = enable? sda_reg : sda;