Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 module test2( data_in, clock, wen, ce, addr, data_out ); input [15:0]data_in; input clock; input wen; input ce; input [5:0]addr; output [15:0]data_out; myram a1 ( .a(addr), // input [5 : 0] a .d(data_in), // input [15 : 0] d .clk(clock), // input clk .we(wen), // input we .i_ce(ce), // input i_ce .spo(data_out) // output [15 : 0] spo ); endmodule
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 `timescale 1ns/1ps module myram( a, d, clk, we, i_ce, spo ); input [5 : 0] a; input [15 : 0] d; input clk; input we; input i_ce; output [15 : 0] spo; // synthesis translate_off DIST_MEM_GEN_V7_2 #( .C_ADDR_WIDTH(6), .C_DEFAULT_DATA("0"), .C_DEPTH(64), .C_FAMILY("spartan6"), .C_HAS_CLK(1), .C_HAS_D(1), .C_HAS_DPO(0), .C_HAS_DPRA(0), .C_HAS_I_CE(1), .C_HAS_QDPO(0), .C_HAS_QDPO_CE(0), .C_HAS_QDPO_CLK(0), .C_HAS_QDPO_RST(0), .C_HAS_QDPO_SRST(0), .C_HAS_QSPO(0), .C_HAS_QSPO_CE(0), .C_HAS_QSPO_RST(0), .C_HAS_QSPO_SRST(0), .C_HAS_SPO(1), .C_HAS_SPRA(0), .C_HAS_WE(1), .C_MEM_INIT_FILE("no_coe_file_loaded"), .C_MEM_TYPE(1), .C_PARSER_TYPE(1), .C_PIPELINE_STAGES(0), .C_QCE_JOINED(0), .C_QUALIFY_WE(0), .C_READ_MIF(0), .C_REG_A_D_INPUTS(1), .C_REG_DPRA_INPUT(0), .C_SYNC_ENABLE(1), .C_WIDTH(16) ) inst ( .A(a), .D(d), .CLK(clk), .WE(we), .I_CE(i_ce), .SPO(spo), .DPRA(), .SPRA(), .QSPO_CE(), .QDPO_CE(), .QDPO_CLK(), .QSPO_RST(), .QDPO_RST(), .QSPO_SRST(), .QDPO_SRST(), .DPO(), .QSPO(), .QDPO() ); // synthesis translate_on endmodule
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 module ram_top( clk, en, we, addr, oen, data_in, data_out ); input clk, en, we, oen; input [5:0] addr; input [255:0] data_in; output [255:0] data_out; BUFG BUFG_inst ( .O(clk1), // 1-bit output: Clock buffer output .I(clk) // 1-bit input: Clock buffer input ); myram a1 ( .clka(clk1), // input clka .ena(en), // input ena .wea(we), // input [0 : 0] wea .addra(addr), // input [5 : 0] addra .regcea(oen), .dina(data_in), // input [255 : 0] dina .douta(data_out) // output [255 : 0] douta ); endmodule
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 module testbench; // Inputs reg clk; reg en; reg we; reg [5:0] addr; reg oen; reg [255:0] data_in; // Outputs wire [255:0] data_out; // Instantiate the Unit Under Test (UUT) ram_top uut ( .clk(clk), .en(en), .we(we), .addr(addr), .oen(oen), .data_in(data_in), .data_out(data_out) ); always begin clk = 1'b0; #4; clk = 1'b1; #4; end initial begin en = 1'b1; oen = 1'b0; //#107; #105; data_in = 256'ha000000000000b000000000000c000000000000000000d0000000000000000e0; we = 1'b1; addr = 6'b000011; //#15; #8; data_in = 256'h000000f0000000000e000000000d00000000c0000000000b00000000000a0000; we = 1'b1; addr = 6'b001001; //#15; #8; data_in = 256'h000000100000000001011111000d000000001000000000010000000000010000; we = 1'b1; addr = 6'b111001; //#15; #8; oen = 1'b1; we = 1'b0; addr = 6'b000011; //#15; #8; we = 1'b0; addr = 6'b111001; #8; we = 1'b0; addr = 6'b100001; #8; we = 1'b0; addr = 6'b001001; //#15; #8; end endmodule
Uh, 3 ns is not the pipeline delay that is the approximate clock period, which isn't the same thing.and why it takes so long (about 2 or 3 clocks) for each output(from an address) to be stable?
when the max frequency is 350MHz I think I should have output for each address in about 3ns! but it didn't happen!
I also don't get why you have so many extra transitions of bit in your data_out bus not aligned with any clock edges?
tanish said:... post place and route simulation ...
wire [255:0] data_out;
Code:wire [255:0] data_out;
This is multiple DMEMs/registers with various simulated routing delays for this large bus.
Uh, 3 ns is not the pipeline delay that is the approximate clock period, which isn't the same thing.
1 clock to capture the address and read enable
1 clock to read the memory array and load it into the output buffer register
So there is a two clock delay to get read data from the RAM, which you then capture on the third clock cycle.
Also why are you using the falling edge of the clock instead of the normal rising edge of a clock? I also don't get why you have so many extra transitions of bit in your data_out bus not aligned with any clock edges?
my point was that you have a wide data bus and you are modeling the delays from elements that might be spread out a little bit. If you expand the bus you'll likely see each bit transitions one time, but with a different delay compared to other bits. As a result, the combined bus shows many transitions.
Actually I have another question.
If I try a code like this at asic does it have a long transiton like this?or does it happen just in FPGAs?
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