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Insertion loss budget on PCB - PCIe Gen 3

engr_joni_ee

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I found this article which deals with the insertion loss budget for PCIe. I am looking for the table in which the total channel insertion loss budget for PICe Gen 3 (8 GT/s) is 22 dB which is distributed as Root Package (3.5 dB), CEM Connector (1.7 dB), Add-in Card (6.5 dB), Remaining Budget for System Base Board (10.3 dB).


Remaining Budget for System Base Board (10.3 dB): Is that the budget for PCB design ? Does it means that the PCB traces should not have more then 10.3 dB insertion loss ?
 
That's what it says and you will not get even close to that with std FR-4 . Also the article legend is reverse assigned.
1704316958749.png

--- Updated ---

To determine the signal attenuation of standard FR4 and its alternatives up to 16 GHz, we need to consider several factors. Signal attenuation in PCB materials is primarily due to dielectric losses and conductor losses, which include both resistive and skin effect losses.

Standard FR4:
- FR4 is a commonly used PCB material with a dielectric constant (Dk) typically around 4.5 at 1 MHz, but this value can vary with frequency. The dissipation factor (Df) for FR4 is relatively high compared to other high-frequency materials, usually in the range of 0.02 at 1 GHz, which can lead to significant signal attenuation at higher frequencies.
- As frequency increases, the dielectric losses in FR4 increase due to its Df, and the skin effect causes the conductor losses to rise, resulting in higher attenuation. At frequencies up to 16 GHz, the attenuation can become quite pronounced, though the exact value will depend on the specific type of FR4 and the dimensions of the conductors.

Alternative Materials:
Several high-frequency materials offer lower attenuation compared to FR4:
1. Rogers RO4000 Series: These materials, such as RO4350B, have a lower Dk and Df compared to FR4. For example, RO4350B has a Dk of around 3.48 and a Df of 0.0037 at 10 GHz.
2. Taconic RF Series: These materials are also designed for high-frequency applications, with lower loss characteristics compared to FR4. Taconic's RF-35 has a Dk of about 3.5 and a Df of 0.0018 at 10 GHz.
3. Isola I-Tera: I-Tera MT40 has a Dk of 3.45 and a Df of 0.0035 at 10 GHz, which is better than FR4 for high-frequency applications.
4. Arlon Microwave Materials: Arlon's 25N has a Dk of 3.38 and a Df of 0.0025 at 10 GHz.

Comparison:
- When comparing these materials to standard FR4, the key differences come down to the Df at high frequencies. Lower Df translates into lower signal attenuation.
- Rogers, Taconic, Isola, and Arlon materials are specifically designed to maintain signal integrity at microwave frequencies and will typically outperform FR4 in applications above a few GHz.
- The choice between these materials will depend on the specific requirements of your application, including the acceptable levels of signal loss, the environmental conditions, and cost considerations.

warmest regards,
GPT 4.0
 
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I am referring to this post regarding "losses in PCB". It shows that in FR4 the losses including conductor loss and dielectric loss are around 0.5 dB/inch at 10GHz.


How we can say that standard FR4 is not suitable for PCIe Gen 3 board design ? Should not it work for 5 inches long trace ? as we know that insertion loss board design budget is around 10 dB from the first post.
 

    FvM

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Regarding 0.5 dB/m, MT40 is not FR-4, it's special low-loss RF substrate. PCIe Gen 3 is 4 GHz, not 10 GHz fundamental frequency.

FR-4 can be used, depending on maximal trace length.
 
If you read the datasheets you will understand loss tangent and reduction of Dk with rising f starting at ~ 900 MHz causes considerable loss. At 16 GHz it would be on the order of several dB / cm with dispersion as well from eddy currents and surface roughness. We used Getek which costs 10% more but 10% of loss tangent of Std FR4 at 928 MHz for this reason. It might be useable to a few GHz only but very lossy.

PCI Gen 3 can be more than 4GHz as stated in your article, which demands a special substrate dielectric and surface conductor polished and gold plated. It neglected to talk about surface roughness, which causes eddy currents from skin depth.

1704400125090.png


Ref : https://www.kingston.com/en/blog/pc-performance/pcie-gen-4-explained

Another fault in the article, is that they mentioned Nyquist f is 1/2 of the bit rate yet Nyquist rule only means you get a random sample of 1 per cycle which does not restore the amplitude of that frequency so it will be seriously attenuated , thus equalization and over sampling is critical to eye pattern margin and resulting BER. Dispersion cannot be reduced by EQ and only by high end substrates like ceramic , teflon or others I stated.
I would expect for good performance at 16GB/s you would be looking for PCB that performs well at 32 GHz for dispersion and eddy currents so that EQ can compensate with < 10 dB loss at 16GHz ( 2x Nyquist rate.)
 
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Yes that is true. I presented the numbers for I-Meta MT 40.

In case of 370 HR (dielectric constant 3.9, loss tangent 0.025) only the dielectric losses are 1.15 dB/inch at 10 GHz and 2.30 dB/inch at20 GHz which when combine with the conductor losses (around 0.4 dB/inch at 10 GHz) would not make it suitable to design longer traces for 8 GHz.

The dielectric losses in I-Meta MT40 (0.13 dB/inch at 10 GHz and 0.26 dB/inch at 20 GHz) are much lower then the dielectric losses in 370 HR (1.15 dB/inch at 10 GHz and 2.30 dB/inch at 20 GHz).
 
Post #5 seems to suggest that bandwidth of PCIe Gen3 differential pair is increased with lane count, but of course it's not., it's keeping 8 Gbps bit rate respectively 4 GHz fundamental frequency. Bandwidth requirement to reproduce the trapezoidal waveform with sufficient eye opening is a bit higher, but not much.
 
I also have heard that PCIe Gen3 is 8 Gbps per lane with 4 GHz as fundamental frequency. But what is X1/X2/X4/X8/X16 ? Are these lanes in Post #5 ?
 
Alright now I understand. PCIe Gen 3 (X1 one lane) is 1 GByte/s which is 8 Gbps for one lane. The fundamental frequency is 4 GHz per lane.
 
Std FR-4 is just a Fire Retardant rating and has nothing to do with electrical properties like Dk and low Df.

370HR is lower Df and not std. Surface roughness is unstated and must be state of the art for stated performance.
But Sierra Proto Express is your best choice for boards if you give all the requirements with electrical testing. $$

A triangle wave integrated from dielectric attenuation is down at least 12 dB at the 3rd harmonic and phase shifted by 90 deg.
Dispersion causes scattering and jitter..

GB/s is GBytes/s
Gb/s is 8b/B or 8x faster or 8 GT/s

PCIe Gen 3 operates at 8 GT/s (gigatransfers per second)
for Square wave is
+2.1 dB @ 4 GHz
- 7.44 db at 12 GHz
for Triangle integrated wave if same Vpp = -4.77 dB (rms)

The critical part to simulate this is the Group Delay which gets distorted and cause reduction of eye pattern.
EQ helps to restore linear phase distortion but not non-linear. Time-domain pre-compensation is used to create the EQ for flat group delay, but it is not flat with harmonics.

If one wanted to suppress harmonic content, I would use Raised Cosine EQ LPF.

-
 
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