So, are you asking for the simulation run time or insertion run time?
I am assuming that the question is for the simulation run time.
So consider following scenarios.
1. one controller and all the memories are within 1 step.
2. 2 controller and the memories are divided but here also we have one step in each controller.
Now, scenario 1, if we put all the memories under 1 step then all the memories will be tested in parallel which is the least simulation time.
Even if we insert 2 controllers but again all the memories are under single step underneath 2 controllers, all the memories will be tested parallel.
If we put all the memories under single step, then we can not reduce the simulation run time further and simulation run time will be based on the max memory macro size.