------------------------column scanner-----------------------------------
entity column_1 is
Port (
clk : in STD_LOGIC;
clk2 : out std_logic;
Col : out std_logic_vector(1 downto 0);
C : out STD_LOGIC_VECTOR (3 downto 0));
end collumn_1;
architecture Behavioral of collumn_1 is
signal count : std_logic_vector(15 downto 0);
begin
process (clk)
begin
if clk' event and clk = '1' then
count <= count + 1;
case count(14 downto 13) is
when "00" => C <= "0001"; Col <= "00";
when "01" => C <= "0010"; Col <= "01";
when "10" => C <= "0100"; Col <= "10";
when "11" => C <= "1000"; Col <= "11";
when others => null;
end case;
end if;
end process;
clk2 <= Count(13);
end Behavioral;
----------------------------------------------------------------------------------------------
----------------------HEX_KEY_Decoder--------------------------------
entity hex_Key is
Port ( Key : in STD_LOGIC_VECTOR (3 downto 0);
C : in STD_LOGIC_VECTOR (3 downto 0);
Assert1 : in STD_LOGIC;
R : out STD_LOGIC_VECTOR (3 downto 0));
end hex_Key;
architecture Behavioral of hex_Key is
--signal Temp_k : std_logic_vector(15 downto 0);
signal TeR : std_logic_vector(3 downto 0);
begin
process ( key )
begin
case key is
when "0000" => TER(0) <= C(0);
TeR(1) <= '0';
TeR(2) <= '0';
TeR(3) <= '0';
when "0001" =>
TeR(0) <= C(1);
TeR(1) <= '0';
TeR(2) <= '0';
TeR(3) <= '0';
when "0010" =>
TeR(0) <= C(2);
TeR(1) <= '0';
TeR(2) <= '0';
TeR(3) <= '0';
when "0011" =>
TeR(0) <= C(3);
TeR(1) <= '0';
TeR(2) <= '0';
TeR(3) <= '0';
--
when "0100" => TeR(0) <= '0';
TeR(1) <= C(0);
TeR(2) <= '0';
TeR(3) <= '0';
when "0101" =>
TeR(0) <= '0';
TeR(1) <= C(1);
TeR(2) <= '0';
TeR(3) <= '0';
when "0110" =>
TeR(0) <= '0';
TeR(1) <= C(2);
TeR(2) <= '0';
TeR(3) <= '0';
when "0111" =>
TeR(0) <= '0';
TeR(1) <= C(3);
TeR(2) <= '0';
TeR(3) <= '0';
--
when "1000" =>
TeR(0) <= '0';
TeR(1) <= '0';
TeR(2) <= C(0);
TeR(3) <= '0';
when "1001" =>
TeR(0) <= '0';
TeR(1) <= '0';
TeR(2) <= C(1);
TeR(3) <= '0';
when "1010" =>
TeR(0) <= '0';
TeR(1) <= '0';
TeR(2) <= C(2);
TeR(3) <= '0';
when "1011" =>
TeR(0) <= '0';
TeR(1) <= '0';
TeR(2) <= C(3);
TeR(3) <= '0';
--
when "1100" =>
TeR(0) <= '0';
TeR(1) <= '0';
TeR(2) <= '0';
TeR(3) <= C(0);
when "1101" =>
TeR(0) <= '0';
TeR(1) <= '0';
TeR(2) <= '0';
TeR(3) <= C(1);
when "1110" =>
TeR(0) <= '0';
TeR(1) <= '0';
TeR(2) <= '0';
TeR(3) <= C(2);
when "1111" =>
TeR(0) <= '0';
TeR(1) <= '0';
TeR(2) <= '0';
TeR(3) <= C(3);
when others => null;
end case;
if Assert1 = '1' then
R <= TeR;
else R <= "1111";
end if;
end process;
end Behavioral;
-------------------------------------------------------------------------------------
---------------------ROW Encoder------------------------------------------------
entity row_encoder is
Port ( R : in STD_LOGIC_VECTOR (3 downto 0);
Flag : out STD_LOGIC;
Row : out STD_LOGIC_VECTOR (1 downto 0));
end row_encoder;
architecture Behavioral of row_encoder is
begin
process ( R )
begin
case R is
when "0001" => Row <= "00"; flag <= '1';
when "0010" => Row <= "01"; flag <= '1';
when "0100" => Row <= "10"; flag <= '1';
when "1000" => Row <= "11"; flag <= '1';
when others => null;
end case;
end process;
end Behavioral;
-----------------------------------------------------------------------------------
----------------------Controller-------------------------------------------------
entity controller is
Port ( clk : in STD_LOGIC;
Flag : in STD_LOGIC := '0';
latch : out STD_LOGIC := '0';
valid : out STD_LOGIC := '0');
end controller;
architecture Behavioral of controller is
type statetype is (S0, S1, S2, S3);
Signal state, Next_state : statetype := s0;
signal count : std_logic_vector(17 downto 0);
begin
--process (clk)
--begin
--if clk' event and clk = '1' then
-- count <= Count + 1;
-- end if;
-- end process;
process (clk, state, flag, count)
begin
if clk' event and clk = '1' then
count <= Count + 1;
case state is
when S0 => state <= Next_state;
if flag = '1' then
next_state <= S1;
else
next_state <= S0;
end if;
when S1 => state <= Next_state;
if count(17) = '1' then
if flag = '1' then
next_state <= S2;
else Next_state <= S0;
end if;
else count <= Count + 1;
end if;
when S2 =>
state <= Next_state;
Count <= (others => '0');
latch <= '1';
Valid <= '1';
Next_state <= S1;
when others => null;
end case;
end if;
end process;
end Behavioral;
-----------------------------------------------------------------------------------
--------------------------------latch---------------------------------------------
entity latch is
Port ( D : in STD_LOGIC_VECTOR (3 downto 0);
Col : out STD_LOGIC_VECTOR (1 downto 0);
Row : out STD_LOGIC_VECTOR (1 downto 0);
LD_ena : in STD_LOGIC;
Clk : in STD_LOGIC);
end latch;
architecture Behavioral of latch is
begin
process (clk, Ld_ena)
begin
if clk' event and clk = '1' then
if Ld_ena = '1' then
Row <= D (3 downto 2);
Col <= D (1 downto 0);
end if;
end if;
end process;
end Behavioral;
------------------------------------------------------------------------------------
-------------------------Top Entity----------------------------------------------
entity top_entity_HEX is
Port (
Q : out STD_LOGIC_VECTOR (3 downto 0);
C : out STD_LOGIC_vector(3 downto 0);
Clk : in STD_LOGIC;
assert1 : in STD_LOGIC;
key : in STD_LOGIC_vector(3 downto 0);
valid : out STD_LOGIC);
end top_entity_HEX;
architecture Behavioral of top_entity_HEX is
component collumn_1
Port ( clk2 : out std_logic;
clk : in STD_LOGIC;
Col : out std_logic_vector(1 downto 0);
C : out STD_LOGIC_VECTOR (3 downto 0));
end component;
component row_encoder
Port ( R : in STD_LOGIC_VECTOR (3 downto 0);
Flag : out STD_LOGIC;
Row : out STD_LOGIC_VECTOR (1 downto 0));
end component;
component latch
Port ( D : in STD_LOGIC_VECTOR (3 downto 0);
Col : out STD_LOGIC_VECTOR (1 downto 0);
Row : out STD_LOGIC_VECTOR (1 downto 0);
LD_ena : in STD_LOGIC;
Clk : in STD_LOGIC);
end component;
component controller
Port ( clk : in STD_LOGIC;
Flag : in STD_LOGIC := '0';
latch : out STD_LOGIC := '0';
valid : out STD_LOGIC := '0');
end component;
component hex_key
Port ( Key : in STD_LOGIC_VECTOR (3 downto 0);
C : in STD_LOGIC_VECTOR (3 downto 0);
Assert1 : in STD_LOGIC;
R : out STD_LOGIC_VECTOR (3 downto 0));
end component;
Signal n1, n3 : std_logic_vector(3 downto 0);
Signal n2, n4 : std_logic_vector(1 downto 0);
signal nclk2, n5, n6 : std_logic;
begin
X1: collumn_1 port map (clk => clk, clk2 => nclk2, C => n1, Col => n2);
X2: hex_key port map (key => key, assert1 => assert1, C => n1, R => n3);
X3: Row_encoder port map (R => n3, Row => n4, flag => n5);
X4: Controller port map ( clk => nclk2, flag => n5, valid => valid,latch => n6);
X5: latch port map ( clk => nclk2, Ld_ena => n6, D(1 downto 0) => n2, D(3 downto 2) => n4, Row => Q(3 downto 2), Col => Q(1 downto 0));
end Behavioral;
-----------------------------------------------------------------------------------------------