Input with a lot of "don't care" : if...elsif or array ?

[Sunflare]

Hello everyone,

I need to encode in vhdl a list given to me in the following format (first element of each line is the input, and the second in the output)

0000000-----0--0-0- , 0
111000110-000--0-0- ,3
...

The table has about 3000 elements, many of them with multiple "don't care"
The input is 19bit wide, but even after expanding the '-' I only use 30k or so of the 500k possibilities. Note that I can't change the input format.


I use a python script to parse this list and write the corresponding vhdl code, but now I'm stuck with two possibilities. I first thought about expanding all the '-' and write the whole table as an array, but I'm concerned about spending so many ressources : starting from 3000 lines I finish with a 19bit memory.
The second option would be to use an if...elsif construct and std_match() functions , but I've never used it with so many input bits. Will the synthetiser generate 3000 comparators with a huge mux ? If so I'm not sure I'll see any gain from the array option.


What's your opinion on this ? Right I'm leaning for the second option, but I'm not sure of the result

Thanks in advance

 

[rca]

You could used case/when VHDL keyword.
case your_bus
when 0000000----0000=>a<= 3;
when .....
End case
Pretty simple to transform from the list provided. And the synthesis tool will made the reduction.

 

[Sunflare]

Are you sure about this ?
I thought the case instruction didn't allow for "don't cares" in the input and that only a if...elif with std_match() could do it.

 

[rca]

sure the don't care is allowed.

 

[FvM]

case your_bus
when 0000000----0000=>a<= 3;

I think, you are referring to the new VHDL 2008 "matching case statement" feature.

It uses a case? keyword. There's no don't care case construct in pre-2008 VHDL.