Input Reference Clock for PLL aside from Crystal Oscillator

[itsSAMthing]

Hello everyone.

I'm trying to design a PLL and its almost complete. However I'm thinking of having the input reference frequency inside the chip, so a crystal osc might not be possible.

1. What do you think would be a good type of oscillator I can use as input frequency of PLL?
2. I am thinking of using a Relaxation Oscillator, is there possible issues that I should take note of?
3. Also does keeping the input freq internal have any advantages/applications? I know many applications are trying to use clocks generated in chip, but I am not sure if it is the same for PLL.

Thank you and have a great day! 😁😁

 

[BigBoss]

You can place off-chip components at external PCB, you can build an active oscillator on-chip.
But on-chip oscillator may mess the substrate and analog circuitry-if there is- may be victim.
Therefore mainly IC manufacturers place the CLK oscillators externally.

 

[dick_freebird]

I'd go with a clock-in-a-can XO that works from the same
supply as your PLL. Phase noise will be minimized by a
"square" input (high edge dV/dt) relative to a low amplitude
sine source but beware low input amplitude limits on some
forms of prescaler front end (capacitor-blocked inverter will
like a bang-bang CMOS drive, but a more "RF-y" preamp
might not like to be driven betweem saturation and cutoff.
My limited experience is around the edges of integrated
RF CMOS PLLs, which used autobiased inverters and
dynamic DFFs in the prescaler front ends, while ref clk was
just inverter gain chains until the phase detector.

 

[itsSAMthing]

You can place off-chip components at external PCB, you can build an active oscillator on-chip.
But on-chip oscillator may mess the substrate and analog circuitry-if there is- may be victim.
Therefore mainly IC manufacturers place the CLK oscillators externally.

Thank you good sir. I do know the possible problems on having the CLK on-chip, but just for curiosity sake (and possibly research topic as well) , do you know if there are other possible advantages on using PLL on a relaxation oscillator aside from increased frequency?

 

[BigBoss]

Thank you good sir. I do know the possible problems on having the CLK on-chip, but just for curiosity sake (and possibly research topic as well) , do you know if there are other possible advantages on using PLL on a relaxation oscillator aside from increased frequency?

Matter of fact is not the frequency, the real problem is substrate coupling injected currents.
Oscillators, Charge Pumps and other switching/hard driven elements inject high amount of noise into substrate and if the process cannot prevent these current by any means ( DTI or similar ) these currents may be real trouble.
Unfortunately this phenomena cannot be predicted or simulated. Therefore I would go with external REF_CLK to have less noise and more stability.

 

[dick_freebird]

If your on-chip ground is noisy then an off-chip clock appears
noisy even if it isn't.

All on-chip grounds are noisy to some degree except for simple
continuous-time linears.

A relaxation oscillator is noisier than a triangle wave due to the
harsh discharge stroke, as far as ground noise. I've often used
a bang-bang triangle wave oscillator in DC-DC type chip designs
(but I did not care a bit about noise, with bigger whales to fry).
Still, making your charge and discharge low current and switched
by small devices, is better.

 

[FvM]

Internal RC oscillator with PLL is often used as clock source for micontrollers, e.g. with PIC18 and PIC24 family. Frequency accuracy and jitter performance is however considerably reduced compared to external crystal oscillator. You can expect 1 or 2 % percent absolute frequency accuracy, sufficient for UART interfaces but not ethernet ot full speed USB. You should also expect a certain strain gauge effect. Flexing the PCB might shift the oscillator frequency by several percent.

 

[Warpspeed]

Many of the frequency synthesizer chips do this too.
There is often an internal clock running at well above 100 Mhz which is divided down then locked with a PLL to an external stable crystal reference of much lower frequency.

The reality is, if you want a clean stable clock, it must have some kind of primary resonator of a suitably high Q.
And that has to be external.
Any completely on chip clock that uses just resistors and capacitors and internal delays for timing, is going to be inherently a bit wobbly and jittery.