In circuit refereed as fig6, are parasitic losses included as if they were components. It is a symbolic signal schematic with 3 cap, 3 res and 3 transistors specified. It is a typical schematic where only parameters needed for RF simulation are included, not equal with a real circuit.
As there is no DC design, are these components not specified. Input/Output of this circuit can not be loaded by a DC load as that would affect DC bias.
Serial cap at input and output are therefore assumed as it is a DC voltage at these pins.
A serial cap at input, of any normal value, can not cause the problem you describe, at least not in this circuit. It is more likely related to simulation setup.