verilog testbench inout
I've faced the same problem by using bidirectional like Kirvan is doing. Let's do some logical stuff :
(1) Inout port is bidirectional port, means it's an input port with some part of your design but also the output port of some other part of your design, and you cant assign any value for the design output port, because their values are directly computed from the value of other input port.
Let say a very simple but examplary example, a full adder, in structural modeling. All of us know that the full adder can be archieved by concat 2 half adder, the output signal of the 1st half adder is also the input of the second half adder, however we can't assign any value for this intermediate(inout port) , because its value is driven by 2 global inputs, say a and b.
With ur case, u have to defined the global inputs(one dimension only) and give the value to it, but not the bidiectional one....