inorder reception of TLP packets in FPGA while doing DMA

Thread starter spman
Start date Apr 30, 2014

Status: Not open for further replies.

Apr 30, 2014

spman

Advanced Member level 4

out of order reception of TLP packets in FPGA while doing DMA

Hi,

I have implemented PCI express core with DMA engine (XAPP1052) in a Virtex-6 FPGA. Everything in transmit section (FPGA to PC) is ok and I receive all of the transmitted data in PC software correctly. But there is a problem in receive engine of FPGA while doing DMA from computer to FPGA. After a lot of experiments finally I realized that sometimes TLP packets arrive in wrong order!! Does anyone else have this problem?! What should I do?

Thanks in advance.

Last edited: Apr 30, 2014

Status: Not open for further replies.

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inorder reception of TLP packets in FPGA while doing DMA

spman

Advanced Member level 4

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