amic
Member level 5
the inl/ dnl plots of my dac show no change at 25 deg C and at cold temp. I understand this is becoz at schematic level there is no vth mismatch and so inl is very good ( simulated value - 0.0025LSB).
I guess i will have to do monte carlo to see the actual inl worst value. right ?
Also, I don't know how much layout will add to the mismatch ( in terms of magnitude of inl ) ? Anybody has got any idea?
I guess i will have to do monte carlo to see the actual inl worst value. right ?
Also, I don't know how much layout will add to the mismatch ( in terms of magnitude of inl ) ? Anybody has got any idea?