You can apply a slow input ramp (if differential as in your case you apply Vin+ from High level to low level while Vin- the opposite) and run a transient analysis. Also the ADC digital outputs must drive an ideal 10 bit DAC. The time for the ramp must have such a value that all the codes in the output of the DAC appear. I think that for an 10bit ADC it must be equal to 1024*Tclk.
In this way you will get in the output of the DAC, the input ramp quantized in steps. It is easy then, by comparing the input ramp to the output steps to calculate the INL and DNL (the procedure is written in many textbooks ).
Hope to helped you