What is the best way to do so? In some scenarios, it may b even bigger than this, but pattern remains similar.x(0*64 TO 0*64+15) = '1';
x(1*64 TO 1*64+15) = '1';
x(2*64 TO 2*64+15) = '1';
...
x(15*64 TO 15*64+15) = '1';
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 GENERIC(LLrow: INTEGER := 16); SIGNAL b0 : STD_LOGIC_VECTOR(N*N/4 - 1 downto 0) := (OTHERS => '0') ; variable row : INTEGER RANGE 1 TO N := 1; variable addr2_2 : INTEGER RANGE 0 TO N*N-1 := 0; ... if row <= LLrow then b0(addr2_2 + LLrow-1 downto addr2_2) <= (OTHERS => '1'); row := row + 1; addr2_2 := addr2_2 + N/2; end if;
if row <= LLrow then
b0(addr2_2 + LLrow-1 downto addr2_2) <= (OTHERS => '1');
row := row + 1;
addr2_2 := addr2_2 + N/2;
end if;
This part gives me a headache...plz use signals!
Stop using variables in the synthesizable part of your design. You can do everything with signals.
dpaul... This part gives me a headache...plz use signals!
Stop using variables in the synthesizable part of your design. You can do everything with signals.
I have a very long code using Finite State Machine. Here I attach the code. The code is sequential, so using signal provides output only on the next clock cycle. Also I sometimes need to update the value of an object within the same loop twice, which is not possible with signals, so I use variables.Don't you know if you write VHDL using variables it behaves more like software
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 ---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 14:39:53 07/27/2017 -- Design Name: -- Module Name: FSM_all - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity FSM_all is GENERIC (L : INTEGER := 3; -- L is level of DWT N : integer := 256; -- N x N is image size logN : INTEGER := 8; -- log10(N)/log10(2) gives n bits that can address N LLrow : INTEGER := 16; -- N/2^(L+1) Range (0 TO LLrow-1) word_length : integer := 11); Port ( rst,clk : in STD_LOGIC; i : in STD_LOGIC_VECTOR (7 downto 0); out_en : OUT std_logic; y : out STD_LOGIC_VECTOR (word_length-1 downto 0)); end FSM_all; architecture Behavioral of FSM_all is -- SRA FUNCTION -- function "sra" (l : signed; r : natural) return signed is alias l_a : signed(l'length-1 downto 0) is l; begin return resize(l_a, l_a'length + r)(l_a'length+r-1 downto r); end function "sra"; --- RAM SIGNALS --- TYPE ram_type IS ARRAY (N*N-1 DOWNTO 0) OF STD_LOGIC_VECTOR(word_length-1 DOWNTO 0); SIGNAL RAM1: ram_type; SIGNAL RAM2: ram_type; SIGNAL we1,en1,we2,en2 : STD_LOGIC :='0'; SIGNAL addr1,addr2 : INTEGER RANGE 0 TO N*N-1 := 0; SIGNAL di1,do1,di2,do2 : STD_LOGIC_VECTOR(word_length-1 DOWNTO 0):= (OTHERS => '0'); --- FSM SIGNALS --- TYPE state IS (fill_ram,dwt1d,idwt1d,dwt2d,idwt2d,initialize_SPIHT,load_b0,load_coef,ref_bitstream,sorting,output); SIGNAL pr_state: state; --- DWT SIGNALS --- SIGNAL s1,x2k,s2,s23,s3 : signed(word_length-1 downto 0); --- DEBUGGING SIGNALS --- SIGNAL db_addr : INTEGER RANGE 0 TO N*N/4-1 := 0; --- SPIHT SIGNALS --- ---(N*N/(2**(2*L))-1) L=3,N=256 =>1023 SIGNAL b0 : STD_LOGIC_VECTOR(N*N/4 - 1 downto 0) := (OTHERS => '0') ;--Current block significant SIGNAL b1, b2 : STD_LOGIC_VECTOR(N*N/16 - 1 downto 0);-- b1:if all des sig or not, b2: typeA or B SIGNAL threshold : INTEGER RANGE 0 TO word_length-1; SIGNAL init_thrsh : signed(word_length-1 downto 0) := (OTHERS => '0'); SIGNAL b0_addr : INTEGER RANGE 0 TO N*N/4-1 := 0; begin --- RAM1 INITIALIZATION HERE --- ram1_init : PROCESS(clk) BEGIN if clk'event AND clk = '1' then if en1 = '1' then if we1 = '1' then RAM1(addr1) <= di1; else do1 <= RAM1(addr1); end if; end if; end if; END PROCESS ram1_init; --- RAM2 INITIALIZATION HERE --- ram2_init : PROCESS(clk) BEGIN if clk'event AND clk = '1' then if en2 = '1' then if we2 = '1' then RAM2(addr2) <= di2; else do2 <= RAM2(addr2); end if; end if; end if; END PROCESS ram2_init; ----- FSM STARTS FROM HERE ---- ----- Main Section of FSM ----- Main: PROCESS(clk,rst) ----DWT VARIABLES---- variable di_temp,di_temp1 : STD_LOGIC_VECTOR(word_length-1 downto 0); variable adr,ram_out,ram_out1,alt1,alt5 : STD_LOGIC := '0'; variable ram_out2 : STD_LOGIC_VECTOR(1 downto 0) := "00"; variable addr2_1,addr2_2,addr1_1,addr1_2,addr1_3,addr1_4,a_temp,b_temp : INTEGER RANGE 0 TO N*N-1 := 0; variable v1,v3 : signed(word_length-1 downto 0) := (OTHERS => '0'); variable v2 : signed(word_length-1 downto 0); variable count_1,count : INTEGER RANGE 0 TO 7 := 0; variable row,col1,col2,c_col1,c_col2 : INTEGER RANGE 1 TO N := 1; variable M : INTEGER RANGE 0 TO N := N; variable level : INTEGER RANGE 0 TO 5 := 1; variable thrsh : STD_LOGIC_VECTOR(word_length-2 downto 0); ----SPIHT VARIABLES---- BEGIN IF clk'EVENT AND clk = '1' THEN IF rst = '0' THEN CASE pr_state IS ------- DWT Stages ----------- WHEN fill_ram => -- Take 1D DWT Directly and fill into RAM2 out_en <= '0'; di_temp(word_length-1 downto 8) := (OTHERS => '0'); -- di_temp(5 downto 0) := (OTHERS => '0'); di_temp(7 downto 0) := i; if adr = '0' then adr := '1'; addr1 <= 0; addr2 <= 0; addr2_1 := 0; addr2_2 := M*M/2; ram_out := '0';count := 0; end if; if count = 0 then count := count + 1; elsif alt5 = '1' then s1 <= signed(di_temp1); x2k <= signed(di_temp); v1 := s1 + x2k; s2 <= v1 sra 1; v2 := s1 - x2k; s23 <= v2 sra 1; alt5 := NOT alt5; else alt5 := NOT alt5; di_temp1 := di_temp; end if; s3 <= s23; if ram_out = '0' then if count_1 >= 6 then we2 <= '1'; en2 <= '1'; di2 <= std_logic_vector(s2); addr2 <= addr2_1; addr2_1 := addr2_1 + 1; ram_out := '1'; else count_1 := count_1 + 1; end if; else we2 <= '1'; en2 <= '1'; addr2 <= addr2_2; addr2_2 := addr2_2 + 1; di2 <= std_logic_vector(s3); ram_out := '0'; if addr2_2 = M*M then pr_state <= dwt2d; alt5 := '0'; count_1 := 0; adr := '0'; s1 <= (OTHERS => 'Z');s2 <= (OTHERS => 'Z'); s3 <= (OTHERS => 'Z'); x2k <= (OTHERS => 'Z'); end if; end if; WHEN dwt1d => out_en <= '0'; we1 <= '0'; if adr = '1' then addr1 <= 0; count := 0; adr := '0';a_temp := 0; addr2_1 := 0;col1 := 1; addr2_2 := M*M/2;row := 1; ram_out := '0';alt5 := '0'; di_temp1 := (OTHERS => 'Z'); elsif col1 <= M then if row < M then if row = 1 then a_temp := addr1; end if; addr1 <= addr1 + 1; row := row + 1; else row := 1; if col1 < M then addr1 <= a_temp + N; end if; col1 := col1 + 1; end if; end if; if count <= 1 then count := count + 1; elsif alt5 = '1' then s1 <= signed(di_temp1); x2k <= signed(do1); v1 := s1 + x2k; s2 <= v1 sra 1; v2 := s1 - x2k; s23 <= v2 sra 1; alt5 := NOT alt5; else alt5 := NOT alt5; di_temp1 := do1; end if; s3 <= s23; if ram_out = '0' then if count_1 >= 6 then we2 <= '1'; en2 <= '1'; di2 <= std_logic_vector(s2); addr2 <= addr2_1; addr2_1 := addr2_1 + 1; ram_out := '1'; else count_1 := count_1 + 1; end if; else we2 <= '1'; en2 <= '1'; addr2 <= addr2_2; addr2_2 := addr2_2 + 1; di2 <= std_logic_vector(s3); ram_out := '0'; if addr2_2 = M*M then pr_state <= dwt2d; alt5 := '0'; count_1 := 0; end if; end if; WHEN dwt2d => out_en <= '0'; we2 <= '0'; if adr = '0' then addr2 <= 0; row := 1; col1 := 1; adr := '1'; addr1_1 := 0; addr1_2 := M*N/2; addr1_3 := M/2; addr1_4 := M*(N+1)/2; ram_out := '0'; count_1 := 0;count := 0; s3 <= (OTHERS => 'Z'); elsif row < M then row := row + 1; addr2 <= addr2 + M/2; elsif row = M then if col1 < M/2 then col1 := col1 + 1; addr2 <= col1 - 1; row := 1; elsif col1 = M/2 then col1 := col1 + 1; col2 := 1; addr2 <= M*M/2; row := 1; else if col2 < M/2 then col2 := col2 + 1; addr2 <= M*M/2 + col2-1; row := 1; end if; end if; end if; if count <= 1 then count := count + 1; elsif alt5 = '1' then s1 <= signed(di_temp1); x2k <= signed(do2); v1 := s1 + x2k; s2 <= v1 sra 1; v2 := s1 - x2k; s23 <= v2 sra 1; alt5 := NOT alt5; else alt5 := NOT alt5; di_temp1 := do2; end if; s3 <= s23; if s23(word_length-1) = '0' then if s23 > v3 then v3 := s23; end if; end if; if s2(word_length-1) = '0' then if s2 > v3 then v3 := s2; end if; end if; init_thrsh <= v3; if ram_out2 = "00" then if count_1 >= 6 then we1 <= '1'; en1 <= '1'; di1 <= std_logic_vector(s2); if c_col1 = 1 then addr1_1 := a_temp; c_col1 := c_col1 + 1; elsif c_col1 = M/2 then a_temp := a_temp + 1; c_col1 := 1; addr1_1 := addr1_1 + N; else c_col1 := c_col1 + 1; addr1_1 := addr1_1 + N; end if; addr1 <= addr1_1; ram_out2 := "01"; else count_1 := count_1 + 1; a_temp := 0; end if; elsif ram_out2 = "01" then we1 <= '1'; en1 <= '1'; addr1 <= addr1_2; ram_out2 := "00"; if c_col2 < M/2 then if c_col2 = 1 then b_temp := addr1_2; end if; c_col2 := c_col2 + 1; addr1_2 := addr1_2 + N; else if addr1_2 = N*(M-1) + M/2 -1 then ram_out2 := "10"; count_1 := 0; c_col1 := 1; c_col2 := 1; alt1 := '0'; else addr1_2 := b_temp + 1; end if; c_col2 := 1; end if; di1 <= std_logic_vector(s3); elsif ram_out2 = "10" then we1 <= '1'; en1 <= '1'; addr1 <= addr1_3; if c_col1 < M/2 then if c_col1 = 1 then a_temp := addr1_3; end if; c_col1 := c_col1 + 1; addr1_3 := addr1_3 + N; else addr1_3 := a_temp + 1; c_col1 := 1; end if; di1 <= std_logic_vector(s2); ram_out2 := "11"; else we1 <= '1'; en1 <= '1'; addr1 <= addr1_4; ram_out2 := "10"; if c_col2 < M/2 then if c_col2 = 1 then b_temp := addr1_4; end if; c_col2 := c_col2 + 1; addr1_4 := addr1_4 + N; else if addr1_4 = N*(M-1) + M - 1 then ram_out2 := "00"; count_1 := 0; if level < L then pr_state <= dwt1d; level := level + 1; alt5 := '0'; M := M/2; else pr_state <= initialize_SPIHT; alt5 := '0';count_1 := 0; level := 1;addr2_2 := 0; addr2 <= 0;row := 1; count := 0;addr2_1 := 0; end if; end if; addr1_4 := b_temp + 1; c_col2 := 1; end if; di1 <= std_logic_vector(s3); end if; ------- SPIHT STAGES ---------------- ------- REFINEMENT PASS ------------- WHEN initialize_SPIHT => if row <= 2*LLrow then b0(addr2_2 + 2*LLrow-1 downto addr2_2) <= (OTHERS => '1'); row := row + 1; addr2_2 := addr2_2 + N/2; if count_1 <= word_length-1 then if init_thrsh(word_length-1-count_1) = '1' then threshold <= word_length-1-count_1; else count_1 := count_1 + 1; end if; end if; else pr_state <= load_b0; end if; addr1 <= 0; WHEN load_b0 => we1 <= '0';we2 <= '0'; if b0_addr < N*N/4 then if b0_addr <= N*N/4-9 then if b0(b0_addr+7 downto b0_addr) = "00000000" then b0_addr <= b0_addr + 8; elsif b0(b0_addr) = '1' then pr_state <= load_coef; else b0_addr <= b0_addr + 1; end if; else if b0(b0_addr) = '1' then pr_state <= load_coef; else b0_addr <= b0_addr + 1; end if; end if; else pr_state <= sorting; b0_addr <= 0; end if; db_addr <= b0_addr; WHEN load_coef => if count = 0 then addr1 <= to_integer(to_unsigned(b0_addr,2*logN) sll 1) + to_integer((to_unsigned(b0_addr,2*logN) srl logN-1) sll logN); elsif count = 2 then addr1 <= addr1 + N - 1; else addr1 <= addr1 + 1; end if; pr_state <= ref_bitstream; WHEN ref_bitstream => if do1(word_length-1) = '1' then di_temp := std_logic_vector(-signed(do1)); else di_temp := do1; end if; if di_temp(threshold) = '1' then ---SIGNIFICANT AT THIS THRESHOLD thrsh := (OTHERS => '0'); thrsh(threshold) := '1'; if di_temp(word_length-2 downto 0) > thrsh then a_temp := 1; else a_temp := 0; end if; if a_temp = 0 then ---NOT ALREADY SIGNIFICANT COEFFICIENT if addr2_1 = word_length-1 then --- can hold only one more bit di_temp1(addr2_1) := do1(word_length-1); di2 <= di_temp1; addr2 <= addr2 + 1; we2 <= '1'; addr2_1 := 0; di_temp1(addr2_1) := di_temp(threshold); addr2_1 := 1; elsif addr2_1 = word_length-2 then di_temp1(addr2_1) := do1(word_length-1); addr2_1 := addr2_1 + 1; di_temp1(addr2_1) := di_temp(threshold); di2 <= di_temp1; addr2 <= addr2 + 1; we2 <= '1'; addr2_1 := 0; else di_temp1(addr2_1) := do1(word_length-1); addr2_1 := addr2_1 + 1; di_temp1(addr2_1) := di_temp(threshold); addr2 <= addr2 + 1; we2 <= '0'; end if; else ---- ALREADY SIGNIFICANT COEFFICIENT di_temp1(addr2_1) := di_temp(threshold); if addr2_1 = word_length-1 then di2 <= di_temp1; addr2 <= addr2 + 1; we2 <= '1'; addr2_1 := 0; else addr2_1 := addr2_1 + 1; we2 <= '0'; end if; end if; else --- NOT SIGNIFICANT AT THIS THRESHOLD di_temp1(addr2_1) := di_temp(threshold); if addr2_1 = word_length-1 then di2 <= di_temp1; addr2 <= addr2 + 1; we2 <= '1'; addr2_1 := 0; else addr2_1 := addr2_1 + 1; we2 <= '0'; end if; end if; if count = 3 then pr_state <= load_b0; b0_addr := b0_addr + 1; count := 0; else count := count + 1; pr_state <= load_coef; end if; pr_state <= sorting; WHEN sorting => pr_state <= idwt1d; -------- IDWT STAGES ---------------- WHEN idwt1d => we1 <= '0';en1 <= '1'; out_en <= '0'; if adr = '1' then ram_out2 := "00"; adr := '0'; ram_out1 := '0'; count_1 := 0;count := 0; addr1_1 := 0; addr1_2 := M*N/2; addr1_3 := M/2; addr1_4 := M*(N+1)/2; addr2 <= 0;a_temp := 0; alt1 := '0';c_col2 := 1; c_col1 := 1; alt5 := '0'; -- s1 <= (OTHERS => 'Z'); do1 <= (OTHERS => 'Z');do1 <= (OTHERS => 'Z'); end if; if ram_out2 = "00" then we1 <= '0'; en1 <= '1'; if c_col1 = 1 then addr1_1 := a_temp; c_col1 := c_col1 + 1; elsif c_col1 = M/2 then a_temp := a_temp + 1; c_col1 := 1; addr1_1 := addr1_1 + N; else c_col1 := c_col1 + 1; addr1_1 := addr1_1 + N; end if; addr1 <= addr1_1; ram_out2 := "01"; elsif ram_out2 = "01" then we1 <= '0'; en1 <= '1'; addr1 <= addr1_2; ram_out2 := "00"; if c_col2 < M/2 then if c_col2 = 1 then b_temp := addr1_2; end if; c_col2 := c_col2 + 1; addr1_2 := addr1_2 + N; else if addr1_2 = N*(M-1) + M/2 -1 then ram_out2 := "10"; c_col1 := 1; c_col2 := 1; alt1 := '0'; else addr1_2 := b_temp + 1; end if; c_col2 := 1; end if; elsif ram_out2 = "10" then we1 <= '0'; en1 <= '1'; addr1 <= addr1_3; if c_col1 < M/2 then if c_col1 = 1 then a_temp := addr1_3; end if; c_col1 := c_col1 + 1; addr1_3 := addr1_3 + N; else addr1_3 := a_temp + 1; c_col1 := 1; end if; ram_out2 := "11"; else we1 <= '0'; en1 <= '1'; addr1 <= addr1_4; ram_out2 := "10"; if c_col2 < M/2 then if c_col2 = 1 then b_temp := addr1_4; end if; c_col2 := c_col2 + 1; addr1_4 := addr1_4 + N; else if addr1_4 = N*(M-1) + M - 1 then ram_out2 := "11"; else addr1_4 := b_temp + 1; c_col2 := 1; end if; end if; end if; if count <= 1 then count := count + 1; elsif alt5 = '1' then s1 <= signed(di_temp1); x2k <= signed(do1); s2 <= s1 + x2k; s23 <= s1 - x2k; alt5 := NOT alt5; else alt5 := NOT alt5; di_temp1 := do1; end if; s3 <= s23; if count_1 >= 6 then we2 <= '1'; if ram_out = '0' then di2 <= std_logic_vector(s3); ram_out := '1'; else di2 <= std_logic_vector(s2); ram_out := '0'; end if; if count_1 <= 7 then count_1 := count_1 + 1; addr2 <= 0; else if row < M then row := row + 1; addr2 <= addr2 + M/2; elsif row = M then if col1 < M/2 then col1 := col1 + 1; addr2 <= col1 - 1; row := 1; elsif col1 = M/2 then col1 := col1 + 1; col2 := 1; addr2 <= M*M/2; row := 1; else if col2 < M/2 then col2 := col2 + 1; addr2 <= M*M/2 + col2-1; row := 1; elsif col2 = M/2 then pr_state <= idwt2d; end if; end if; end if; end if; else count_1 := count_1 + 1;we2 <= '0'; row := 1;col1 := 1;col2 := 1;ram_out := '0'; end if; WHEN idwt2d => out_en <= '0'; we2 <= '0'; if adr = '0' then adr := '1'; addr1 <= 0; addr1_1 := 0; addr2 <= 0; count_1 := 0; count := 0; col1 := 1; addr2_1 := 0;alt5 := '0'; addr2_2 := M*M/2;alt5 := '0'; ram_out := '0';col1 := 1;ram_out1 := '0'; end if; if ram_out = '0' then addr2 <= addr2_1; addr2_1 := addr2_1 + 1; ram_out := '1'; else addr2 <= addr2_2; if addr2_2 = M*M-1 then ram_out := '1'; else addr2_2 := addr2_2 + 1; ram_out := '0'; end if; end if; if count <= 1 then count := count + 1; elsif alt5 = '1' then s1 <= signed(di_temp1); x2k <= signed(do2); s2 <= s1 + x2k; s3 <= s1 - x2k; alt5 := NOT alt5; else alt5 := NOT alt5; di_temp1 := do2; end if; if count_1 >= 6 then we1 <= '1';en1 <= '1'; if ram_out1 = '0' then di1 <= std_logic_vector(s2); ram_out1 := '1'; else di1 <= std_logic_vector(s3); ram_out1 := '0'; end if; if count_1 <= 6 then count_1 := count_1 + 1; addr1 <= 0; elsif col1 <= M then if row < M then if row = 1 then a_temp := addr1; end if; addr1 <= addr1 + 1; row := row + 1; else row := 1; if col1 < M then addr1 <= a_temp + N; end if; col1 := col1 + 1; end if; else if level = L then pr_state <= output; else pr_state <= idwt1d; level := level + 1; M := 2*M; end if; end if; else count_1 := count_1 + 1; addr1 <= 0;a_temp := 0;row := 1; alt1 := '0'; col1 := 1; end if; ----- OUTPUT STAGES ------ WHEN output => out_en <= '1'; we1 <= '0';en1 <= '1'; if do1(word_length-1) = '1' then y <= (OTHERS => '0'); else y(word_length-1 downto 0) <= do1(word_length-1 downto 0); end if; if alt1 = '0' then addr1_1 := 0; alt1 := '1'; else addr1_1 := addr1_1 + 1; if addr1_1 = N*N then pr_state <= fill_ram; end if; end if; addr1 <= addr1_1; END CASE; END IF; END IF; END PROCESS Main; end Behavioral;
I have to initialize a very long vector in the pattern such as
What is the best way to do so? In some scenarios, it may b even bigger than this, but pattern remains similar.
This is not good. Allow extra states (I am sure your design can live with 2 or 3 clks of extra latency), let the signals update on the next clk, and then check their values in a new state.Also I sometimes need to update the value of an object within the same loop twice, which is not possible with signals, so I use variables.
Why don't you use a generate statement to achieve the above(assuming x is a signal of type std_logic_vector)?
array_gen : for i in 0 to 15 generate
x(i*64 TO i*64+15) <= (others => '1');
end generate array_gen;
We use cookies and similar technologies for the following purposes:
Do you accept cookies and these technologies?
We use cookies and similar technologies for the following purposes:
Do you accept cookies and these technologies?