kumar_eee
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module top (clk, out);
input clk;
reg [7:0] mem [0:255];
reg [7:0] addr;
output reg [7:0] out;
integer x;
initial begin
addr = 'h55;
for (x=0; x<256; x=x+1)
mem[x] = {x[0],x[1],x[2],x[3],x[4],x[5],x[6],x[7]}; // reversed bits
end
always @ (posedge clk) begin
addr <= addr + 1;
out <= mem[addr];
end
endmodule
noloser said:is there a good way to know which operation is synthesizeable while which do not (for both vhdl & verilog)?
noloser said:How about the use of arithmetic operation (+-/*) within a VHDL module/process; are such operation synthesizable or is it only for simulation purpose.
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