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Information about GPS sensitivity development

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jcpu

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Hi, I am looking for literature / material for the following question:

For ~10 years, the GPS receiver sensitivity improved from ~-140 dBm
to ~-160 dBm. The noise figure of RF receiver part remain similar < 1.5dB.
And seems the difference is in DSP correlator part.

To my knowledge, older GPS digital chip, say GP2021, deploys 12 correlators,
(number of correlator has not so much to do with sensitivity, I suppose)
and each correlator has 25 bit resolution CODE DCO, 26 bit resolution
carrier DCO.

Can someone teach, happened to those DSP that improved the sensitivity
by ~20 dB?
 

jcpu

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gps sensitivity dbm

Well, I am getting some clue here:

Using 0.11 micron CMOS technology, Fujitsu Microelectronics America, Inc. has released a new chipset for the high-sensitivity GPS/AGPS receivers required in communications systems that support telematics and navigation applications for mobile location, tracking and monitoring.

According to Fujitsu, this chipset achieves the industry's highest levels of sensitivity, accuracy and time-to-first-fix (TTFF) with low power and a small PCB footprint. It consists of a baseband chip, the MB87Q2040, which interfaces to a host CPU/MCU via an UART serial interface; and an RF front-end chip, the MB15H156, which supports GPS L-band C/A code. Capable of operating in both "autonomous GPS/standalone" mode and "assisted GPS" mode, the chipset supports leading air interfaces, including UMTS/WCDMA, GSM/GPRS, PDC and CDMA. The chipset is also versatile: A receiver can be initially developed as an autonomous GPS receiver and subsequently upgraded through software to AGPS when assistance becomes available.

Fujitsu said that the new chipset has been developed specifically to meet the industry's requirements for low power, small footprint, and reduced materials costs. The MB87Q2040 baseband chip incorporates highly optimized GPS/AGPS baseband IP that has been licensed from eRide Inc., based in San Francisco. eRide's patented and proven GPS/AGPS IP is based on the company's extensive experience in the GPS market. Using power-saving techniques with the 0.11 micron technology results in a peak baseband power dissipation of only 67 mW during low signal strength acquisition, while power dissipation is less than 40 mW while continuous tracking is at a 1Hz update rate. The acquisition/tracking engine on the chip has 44,000 effective correlators, resulting in high indoor sensitivity calibrated to -157.5 dBm, with indoor accuracy of <20 m. The chipset meets FCC-E911 requirements for October 2005 and achieves fast TTFF of <1 second when hot and around 32 seconds when cold for outdoor fixes.

The MB15H156 RF front-end chip is built using Fujitsu's biCMOS process, which integrates most RF externals, and features on-chip IF-filters, VCO, PLL, oscillators and LNA. The result is a low BOM cost and component count that also minimizes board area.

Fujitsu provides a software library for interfacing to the application software layer. The control software on the host CPU is processor- and OS-independent, running as a single thread requiring no real-time interrupts, RTOS or host libraries.

The MB87Q2040 and MB15H156 are sampling now in 7 mm x 7 mm 48-pin and 5 mm x 5 mm 32-pin BCC plastic packages, respectively, with pin pitch at 0.5 mm, delivering a total footprint of below 100 mm2. The chipset operates over the industrial temperature range of -40Cto +85C.

Now, could someone teach me what 44,000 effective correlators means in terms of circuit design terminology?
 

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gps sensitivity *dbm

I found the answer, and let's share this:
They increase the corellator integration time

Now could someone help me,
what 44,000 effective correlators is?

Thanks
 

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