llibrary ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity lcd_driver is
port (
clock_50mhz : in std_logic;
key : in std_logic; --sw[0]
clock_500hz: inout std_logic;
LCD_EN,LCD_RS,LCD_RW,LCD_ON,LCD_BLON :out std_logic;
LCD_DATA :out std_logic_vector (7 downto 0);
ledg: out std_logic
);
end entity lcd_driver;
architecture a_lcd_driver of lcd_driver is
signal D0:std_logic;
signal count_50mhz: std_logic_vector(27 downTO 0);
type statetype is (s0,s1,s2,s3,s4,s5,s6,s7,s8,s9,s10,s11,s12,s13,s14,s15,s16,s17);
signal state,nextstate : statetype;
--------------------------------------------
begin
LCD_ON<='1';
LCD_RW<='0';
LCD_BLON<='1';
------------------------------------------------------------clock division---------
process (clock_50mhz,key)
begin
if (key='0') then
count_50mhz<=X"0000000";
elsif rising_edge(clock_50mhz) then
if (count_50mhz = X"186A0") then
count_50mhz <= X"0000000";
else
count_50mhz <= count_50mhz + "1";
end if;
end if;
end process;
process (clock_50mhz,key)
begin
if (key='0') then
D0<='0';
elsif rising_edge(clock_50mhz) then
if (count_50mhz = X"186A0") then
D0 <= not D0;
end if;
end if;
end process;
ledg <= D0 ;
clock_500hz <= D0;
--=============================================================================
-- Sequential Logic of FSM
process (clock_500hz,key)
begin
if key='0' then
state<=s0;
elsif rising_edge(clock_500hz) then
state<=nextstate;
end if;
end process;
-------------------------------------------------------------------------------
--=============================================================================
-- Next State Decoder of FSM
process (state)
begin
case state is
when s0 => nextstate <= s1;
when s1 => nextstate <= s2;
when s2 => nextstate <= s3;
when s3 => nextstate <= s4;
when s4 => nextstate <= s5;
when s5 => nextstate <= s6;
when s6 => nextstate <= s7;
when s7 => nextstate <= s8;
when s8 => nextstate <= s9;
when s9 => nextstate <= s10;
when s10 => nextstate <= s11;
when s11 => nextstate <= s12;
when s12 => nextstate <= s13;
when s13 => nextstate <= s14;
when s14 => nextstate <= s15;
when s15 => nextstate <= s16;
when s16 => nextstate <= s17;
when s17 => nextstate <= s0;
when others => nextstate <= s0;
end case;
end process;
-------------------------------------------------------------------------------
--=============================================================================
-- Output Logic of FSM
process (clock_500hz,key)
begin
if key='0' then
LCD_DATA <=X"00";
LCD_RS <='0';
LCD_EN <='0';
elsif rising_edge(clock_500hz) then
case (nextstate) is
when s0 => LCD_DATA <=X"38";
LCD_RS <='0';
LCD_EN <='1';
when s1 => LCD_EN <= '0';
when s2 => LCD_DATA <=X"38";
LCD_EN <='1';
when s3 => LCD_EN <='0';
when s4 => LCD_DATA <=X"38";
LCD_EN <='1';
when s5 => LCD_EN <='0';
when s6 => LCD_DATA <=X"08";
LCD_EN <='1';
when s7 => LCD_EN <='0';
when s8 => LCD_DATA <=X"01";
LCD_EN <='1';
when s9 => LCD_EN <='0';
when s10 => LCD_DATA <=X"0F";
LCD_EN <='1';
when s11 => LCD_EN <='0';
when s12 => LCD_DATA <=X"84";
LCD_EN <='1';
when s13 => LCD_EN <='0';
when s14 => LCD_DATA <=X"80";
LCD_EN <='1';
when s15 => LCD_EN <='0';
when s16 => LCD_DATA <=X"22";
LCD_RS <='1';
LCD_EN <='1';
when s17 => LCD_EN <='0';
when others => LCD_DATA <=X"00";
LCD_RS <='0';
LCD_EN <='0';
end case;
end if;
end process;
-------------------------------------------------------------------------------
-- LCD_ON<='1';
--LCD_RW<='0';
--LCD_BLON<='1';
end a_lcd_driver;