(* USE_DSP48="YES" *)
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Engineer: John *****
// Create Date: 22:24:29 05/02/2011
// Module Name: tap
// Project Name:
// Target Devices: Atlys Board - Spartan6(XC6SLX45)
// Description: Infer DSP48A1 Slice - Systolic FIR Tap w/ Coeff Input
// addout = (xin * win) + addin
//////////////////////////////////////////////////////////////////////////////////
module tap(
input clk,
input rst,
input ce,
input signed [17:0] xin,
input signed [17:0] wn,
input signed [47:0] addin,
output signed [17:0] xout,
output signed [47:0] addout
);
//Pipeline registers
reg signed [35:0] M;
reg signed [47:0] accum;
reg signed [17:0] xin_r;
reg signed [47:0] addin_r;
//addout = (xin * win) + addin
always@(posedge clk) begin
if(rst) begin
M <= 0;
accum <= 0;
xin_r <= 0;
xin_r_r <= 0;
wn_r <= 0;
addin_r <= 0;
end
else if(ce == 1'b1)
begin
xin_r <= xin;
wn_r <= wn;
M <= xin_r * wn_r;
accum <= M + addin;
end
end
assign addout = accum;
assign xout = xin_r;
endmodule