If the plot the impedance phase of a (non-ideal) capacitor is plotted and seen to approach -90 degrees, is it acceptable to infer that the ESL is negligible?
Dear tasctasc
Hi
If you consider just a few nano henry for ESL , what will think ? of course it is inconsiderable ! ( at low frequencies ) ( but if you increase the frequency of operation as large as some MHZ , you'll see the effect !
Best Wishes
Goldsmith
Dear tasctasc
Hi
If you consider just a few nano henry for ESL , what will think ? of course it is inconsiderable ! ( at low frequencies ) ( but if you increase the frequency of operation as large as some MHZ , you'll see the effect !
Best Wishes
Goldsmith
Which software you're referring to ? many of softwares has not any consideration for ESL and ESR . you have to add it externally . i though you are testing that in practice !
Hi Goldsmith,
I both simulated using spectre in cadence and measured on-chip (the measured results are very different from simulated). The capacitors are MOS capacitors. In both cases the impedance decreases in the frequency range of interest and does not rise, which I assumed to mean that the ESL is small. Again, in both cases, the impedance phase approaches -90, again which I assume means ESL is small.
So now the two questions are:
1) Is it acceptable to assume ESL~0?
2) Why the big discrepancy in measred vs. simulated results?
Which software you're referring to ? many of softwares has not any consideration for ESL and ESR . you have to add it externally . i though you are testing that in practice !
Hi again , the reason of these different can be because of your capacitor type ! try to do the same with a 1000uf ( usual type ) capacitor . and show me the result . i bet that it is interesting ! ( by the way , if you get high value of instantaneous current from your cap , the result will be pretty different ! i saw this effect in my transmitters .
And don't forget that simulation can't show you many of events !
Good luck
Goldsmith