Hi,
I created an 8bit Barrel Shifter and now I want to simulate it using Xilinx ISE tools, specifically I want to do a Post-Route simulation (the last step).
I do these steps:
1. Synthesize - XST
2. Implement Design
3. I check the "Synthesis Report" and find: "Minimum period: 3.281ns (Maximum Frequency: 304.785MHz)"
Now when I create a test bench and set the clock period to 10ns (100MHz) it works fine.
Then when I set the clock period to 4ns (250MHz) it doesn't work fine. Here it is a screenshot:
View attachment 84543
Why I get those red signals?