In VHDL Device utilization summary report which things are useful?

[venky.817]

After Executing synthesize, translate, Map and place -route, VHDL generates a device summary utilization report. In that report several things like no.of slice registers, no.of occupied slices, no.of dsp slices, no.of slice LUTs. In those which things i have to concentrate for efficient coding.

 

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VHDL doesn't generate a device summary...the synthesis tool does.

The simple answer is all of the above.

A more complicated answer is whatever is important to you and the design you're implementing.

e.g. design must run at 500 MHz in the FPGA. Then you better have 1-flip-flop 1 LUT pair with no extra LUTs feeding the flip-flop/LUT pair. So you would want to see many more registers than LUTs used.

 

[sureshaa]

Hi Venky.817,
Device utilization summary report is nothing but what the tool understood from your RTL.
1. For simple example If you are trying design one flop, Your tool will show one register. In a case it is showing two flops that means you have added one more register in your design.
2. If your combo logic is more than your register, you can come to know max freq will affect.(Even Before going for Timing Analysis).
I have mentioned only two cases. like that using your device utilization you can learn lot of information.
I hope it is useful for you.