In Pseudo NMOS how the dynamic power is reduced due to less loading effect ?

[mujju433]

Hi everyone,

I would like to know how a dynamic power depends upon the Load capacitance? If this is so then Please let me know how the dynamic power is reduced due to less loading effect in Pseudo NMOS logic.

Does Load capacitance depends upon the NMOS transistors? If this is so then it would be correct, but if it depends upon both PMOS with ground and NMOS then it is becoming confusing for me.

Regards
mujju

 

[praneethrajkanakam]

The Dynamic power consumption occurs during switching

The energy consumed during switching is C V^2
Where C- is the load capacitance; ; Assuming width of n & p type the same we can say that the load offered to the previous stage will be = W (in pseudo)
in normal type it is load id 2W

load (C) is reduced in pseudo so dynamic power is reduced.

The load cap. depends on the the load offered by the wire and also the no. of transistors a particular device is driving. In pseudo, it drives only one transistor whereas in CMOS it drives both p & n mos. For the clarity I added an image of it.

 

[mujju433]

Thanks a lot Praneeth, I understood now.