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In CDR circuit, what is dominant factor contributed to jitter of clock?~~~~~

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In CDR circuit, what is the most dominant factor contributed to jitter of clock?

1. Charge pump current mismatch.

=> Phase Detector UP/DN signal is not wide enough so Charge pump can not switch properly.


2. Ripples of VCO control voltage.
=> Phase Detector UP/DN signal is increased from some topology, so in lock condition

Ripples of VCO control voltage is increased.


can you explain for me? or Can you suggest some paper related to above problem??
 

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