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IMPORTANT VERILOG CODING PROBLEM

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choonlle

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Case A:
always @(ctrl or dataIn0 or dataIn1)
dataOut <= (ctrl) ? dataIn1 : dataIn0;

Case B:
always @(ctrl or dataIn0 or dataIn1)
dataOut = (ctrl) ? dataIn1 : dataIn0;

Which case is correct? WHY?
 

Case A: is correct!
 

    C

    choonlle

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No Case B is correct. Because combinational logic.
 

case B is correct as it is combinational assignment. bcoz for combinational circuit use blocking assignments. h/w in both the cases will be the same.. it only affects simulation

Sachin
 

I make final conclusion :

A is correct !


Finally, i get this answer from Verilog Coding & Synthesis Book.
 

Can you please upload that book
 

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