sandhiyaselvaraj
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Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; -- synthesis translate_off use std.textio.all; use ieee.std_logic_textio.all; -- synthesis translate_on -- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; entity Memory is generic ( WIDTH : integer := 512; HEIGHT : integer := 512; -- IMAGE_MEMORY_SIZE ADDR_BUS_WIDTH : integer := 19; INPUT_FILENAME : string := "TestData.txt"; -- Note: in Test Bench Waveform, file name is -9999, so must be modified OUTPUT_FILENAME : string := "DWTResult.txt" ); port ( cs : in std_logic; rd : in std_logic; wr : in std_logic; dump : in std_logic; addr : in std_logic_vector(ADDR_BUS_WIDTH - 1 downto 0); -- note: IMAGE_MEMORY_SIZE datain : in std_logic_vector(7 downto 0); dataout : out std_logic_vector(7 downto 0) ); end Memory; architecture Behavioral of Memory is -- synthesis translate_off type memory_type is array(0 to WIDTH*HEIGHT - 1) of std_logic_vector(7 downto 0); signal mem : memory_type; -- instance of memory: image data procedure FillMemory(signal omem: out memory_type; file_name: string) is file ifile : TEXT is in file_name; variable l_in : LINE; variable dt : std_logic_vector(7 downto 0); begin for ty in 0 to HEIGHT/2 - 1 loop readline(ifile, l_in); for tx in 0 to WIDTH - 1 loop hread(l_in, dt); omem(tx + WIDTH*ty) <= dt; end loop; end loop; end; -- write imem to file, imem may be signal or variable procedure DumpMemory(imem: in memory_type; file_name: string; lower_addr_half: boolean) is file ofile : TEXT is out file_name; variable l_out : LINE; variable dt : std_logic_vector(7 downto 0); begin if lower_addr_half then for ty in 0 to HEIGHT/2 - 1 loop for tx in 0 to WIDTH - 1 loop dt := imem(tx + WIDTH*ty); hwrite(l_out, dt); write(l_out, ' '); end loop; writeline(ofile, l_out); end loop; else for ty in HEIGHT/2 to HEIGHT - 1 loop for tx in 0 to WIDTH - 1 loop dt := imem(tx + WIDTH*ty); hwrite(l_out, dt); write(l_out, ' '); end loop; writeline(ofile, l_out); end loop; end if; end; -- synthesis translate_on begin -- synthesis translate_off process(cs, rd, wr, dump, addr, datain) variable mem_init : boolean := false; variable reorder_mem : memory_type; begin -- initialize memory content from file if (not mem_init) then mem_init := true; if INPUT_FILENAME'length > 0 then FillMemory(mem,INPUT_FILENAME); end if; end if; -- dump memory to file if (dump'event and dump = '1') then if OUTPUT_FILENAME'length > 0 then DumpMemory(mem,OUTPUT_FILENAME,TRUE); -- write reordered coefs to file DumpMemory(mem,"DWT_VERSD.txt",FALSE); end if; end if; -- read or write respond if (cs = '1') then if (wr = '1') then mem(CONV_INTEGER(UNSIGNED(addr))) <= datain; elsif (rd = '1') then dataout <= mem(CONV_INTEGER(UNSIGNED(addr))); else dataout <= (others => 'Z'); end if; end if; end process; -- synthesis translate_on end Behavioral; file ifile : TEXT is in file_name; file ofile : TEXT is out file_name;
NgdBuild:604 - logical block 'U1' with type 'Memory' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, case mismatch between the block name and the edif or ngc file name, or the misspelling of a type name. Symbol 'Memory' is not supported in target 'spartan3'. This is my error.
I got error in these two lines. kindly reply your solution.
Thanks!