Implementing Simulink Floating-Point Model in FPGA?

[digi001]

Any advice on how I can implement a simulink Floating-Point model in a FPGA?

Should I keep it floating point and try to come up with a way to manage these calculations in the FPGA or change to fixed point?

The algorithm includes non-linear processes (Max,Min), integrations, gains multiplies etc.

 

[TrickyDicky]

floating point uses lots of rousources and has long latencies per module, ranging from about 5-10 clocks for an add to about 50 for a divide or square route.

On an FPGA, you're much better off with fixed point, as the rousource usage and latency is much much lower.

Only go with floating if you really really have to. But most of the time, fixed point is fine.

Are you planning on using HDL coder?

 

[digi001]

Yes floating point adders multipliers etc all take so much more resources on the Altera and Xilinx FPGAs. I think I may not even be able to fit all the math onto the FPGA if I keep everything floating point. I could possibly come up with a strategy to break up identical parallel processes and implement them in a sequential way through a single floating point process for some blocks.

But I am starting to look at complete fixed point implementation. I have access to Fixed-Point Tool and Simulink Fixed Point advisor, but not HDL Coder as of now. I have experience coding my own Verilog so I was planning to do this task manually.

 

[TrickyDicky]

I think you've now just answered your own question really. Floating point IP reuse can be re-used if you have a slow enough data rate and fast enough clock, but the savings with fixed point are huge. Unless you need the huge range floating point offers, fixed will be better, even if you go to stupid sized fixed point.