My board poses an Ethernet connector which I'd like to use it for configuring the FPGA configuration PROM and bypass the JTAG cable.
My idea is to generate PROM configuration file (using Impact) then pass it through LAN cable to embedded CPU which is implemented inside FPGA. Then CPU either directly or through one piece of firmware access PROM and load new configuration file. The dedicated I/O from CPU to PROM are devised.
For doing that I need an implementation of JTAG protocol either in software or in firmware. Any one has any idea, link, document?
Have a look at Xilinx's own XAPP058. This is a fairly standard approach although, in my limited experience, most systems use this approach to program the FPGA directly and therefore eliminate the PROM. The principle remains the same though
Have a look at Xilinx's own XAPP058. This is a fairly standard approach although, in my limited experience, most systems use this approach to program the FPGA directly and therefore eliminate the PROM. The principle remains the same though