implementing DWT and SPIHT compression on FPGA

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vjcro

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DWT and SPIHT in FPGA

Hallo, everybody!

I'm new at this forum and I've been searching for some useful info about implementing a DWT (Haar) and SPIHT compression on FPGA.
I've found some questions, but no answers by now

I've read about SPIHT quite a lot, made a MATLAB code... Now I've started to plan VHDL programming, but I don't have much experience so I could use some practical advice regarding FPGAs...

If somebody has experience with this, I would really appreciate some help.

Thanks,
V.
 

hiii

do u still need help with SPIHT or have you found a solution already. Maybe i can help
 
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    hayfa

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i want code matlab for spiht compression

---------- Post added at 19:04 ---------- Previous post was at 19:02 ----------

want code matlab for spiht or ezw compression
 

try to break down the coding algorithm into sub parts.
pick out the various processing elements you need like:

block ram memory for storage
state markers/dynamic FIFO for LIS LSP LIP
THRESHOLD GENERATOR
ADDRESS GENERATOR BLOCK
COMPARATORS,ADDERS ETC.

Then design a state table to get a more hardware oriented picture of your algo.
after that simply use an fsm based design strategy as it would be the most easiest one to synchronize the various modules.
i haven't tried spiht but i implemented a modified SPECK compression codec on FPGA and believe me this strategy is the most easiest one as it will give you results in just about a few weeks.

for queries you can sent mails at:
syedshakiriqbal@zhcet.ac.in
 
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