library ieee;
use ieee.std_logic_1164.all;
entity RotatingOne is
port(nRESET, CLK, SCK, SI, nCS : in std_logic;
POut : out std_logic_vector(7 downto 0));
end RotatingOne;
architecture shift of RotatingOne is
constant WIDTH : integer := 8;
signal cmd : std_logic_vector(7 downto 0);
signal temp : std_logic_vector(WIDTH - 1 downto 0);
signal rise_SCK, fall_SCK : std_logic;
signal CS_rising, CS_falling : std_logic;
component sync
port(
SCK : in std_logic;
CLK : in std_logic;
rise, fall : out std_logic
);
end component;
begin
sync1 : sync port map(SCK, CLK, rise_SCK, fall_SCK);
sync2 : sync port map(nCS, CLK, CS_rising, CS_falling);
process(CLK, nRESET)
begin
if (nRESET = '0') then
cmd <= (others => '0');
elsif rising_edge(CLK) then
if nCS = '0' then
if rise_SCK = '1' then
cmd <= cmd(WIDTH - 2 downto 0) & SI;
end if;
end if;
end if;
end process;
process(CLK, nRESET)
begin
if (nRESET = '0') then
temp <= (others => '0');
elsif rising_edge(CLK) then
if CS_rising = '1' then
case cmd is
when "00000001" =>
temp <= "00000001";
when "00001111" =>
temp <= "00000000";
when "10101010" =>
temp <= temp(WIDTH - 2 downto 0) & '0';
when others =>
null;
end case;
end if;
end if;
end process;
end shift;
library ieee;
use ieee.std_logic_1164.all;
entity sync is
port(
d : in std_logic;
CLK : in std_logic;
rise_d, fall_d: out std_logic
);
end sync;
architecture sync_arch of sync is
signal sig_rise, sig_fall: std_logic;
begin
sync1: process(CLK)
variable resync: std_logic_vector(1 to 3);
begin
if rising_edge(CLK) then
sig_rise <= resync(2) and not resync(3);
sig_fall <= resync(3) and not resync(2);
resync := d & resync(1 to 2);
end if;
end process;
rise_d <= sig_rise;
fall_d <= sig_fall;
end sync_arch
I get a "Invalid Attachment specified" for the attachment you link to...
process(CLK, nRESET)
begin
if (nRESET = '0') then
cmd <= (others => '0');
SO <= '0';
elsif rising_edge(CLK) then
if cs_falling = '1' then
SO <= cmd(cmd'high);
end if;
if CS_sync = '0' then
if SCK_rising = '1' then
cmd <= cmd(8 - 2 downto 0) & SI;
elsif sck_falling = '1' then
SO <= cmd(cmd'high);
end if;
end if;
end if;
end process;
DO <= SO when cs_sync = '0' else 'Z';
If it's a problem, MISO output enable can be easily controlled asynchronously without affecting the synchronous SPI design operation.However, because cs_sync is delayed, the device will not release the MISO line for a couple of clock cycles. Is this OK?
If it's a problem, MISO output enable can be easily controlled asynchronously without affecting the synchronous SPI design operation.
As more general point, the synchronous slave operation causes a considerable MISO delay, you have to check if it's tolerated by the master controller.
DO <= SO when nCS = '0' else 'Z';
Yes, exactly.If I understand you correctly, this is considered OK because this isn't part of our sequential design but rather combinational.
process(CLK, nRESET)
begin
if (nRESET = '0') then
cmd <= (others => '0');
SO <= '0';
elsif rising_edge(CLK) then
if CS_sync = '0' then
if SCK_rising = '1' then
cmd <= cmd(8 - 2 downto 0) & SI;
end if;
end if;
end if;
end process;
process(CLK, nRESET)
begin
if nRESET = '0' then
out_reg <= (others => '0');
elsif rising_edge(CLK) then
if cs_sync = '0' then
if sck_falling = '1' then
out_reg <= out_reg(out_reg'high - 1 downto out_reg'low) & '0';
end if;
elsif cs_sync = '1' then
if ACK = '1' then
out_reg <= shift_count_vector;
else
out_reg <= (others => '1');
end if;
end if;
end if;
end process;
process(CLK, nRESET)
variable shift_count : integer range 0 to 72;
begin
if (nRESET = '0') then
temp <= (others => '0');
shift_count := 0;
elsif rising_edge(CLK) then
if CS_rising = '1' then
case cmd is
when "00000001" =>
temp <= (others => '0');
temp(0) <= '1';
shift_count := 1;
ACK <= '1';
when "00001111" =>
temp <= (others => '0');
shift_count := 0;
ACK <= '1';
when "10101010" =>
temp <= temp(WIDTH - 2 downto 0) & '0';
shift_count := shift_count + 1;
ACK <= '1';
when others =>
ACK <= '0';
end case;
shift_count_vector <= std_logic_vector(to_unsigned(shift_count,shift_count_vector'length));
end if;
end if;
end process;
Yes, or change the synchronization scheme.So would my only course of action be increasing my system clock?
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