You could take the bit stream, convert it to words, 8-32 bits. You can then store those in a FIFO and take them out on the output side of the FIFO as needed. A FIFO can be implemented in a duel port block RAM. One side is writing the bits, converted to words, and the other side is reading them as needed. This will work as long as your rate of reading is more than your rate or writing.
Here is a link to a web search, FIFO VHDL implementation VHDL Code
""You could take the bit stream, convert it to words, 8-32 bits.""
can you please elaborate this?? for conversion do we need to store is some where and from there we have to take Dword or a byte??? or how can we proceed this?
I only say conver to words because they are easy to store in a FIFO but there is no reason why you could not use a one bit wide FIFO. Just that words (8-32 bits) will use the block RAM more efficiently. So it all depends on if your FPGA is used up, you may want to pack things in more.
To convert a bit stream into words, for each bit that comes in, write that bit to an index in the word. When you have enough bits, ie. counter went to max, you can load the word into the FIFO with a simple write operation.
Code:
signal word : std_logic_vector(7 downto 0);
gen_word:
process(rst, clk)
variable i : integer
begin
if(rst = '1')
i := 0;
write_fifo <= '0';
elsif(clk'event and clk = '1' and "valid") then
write_fifo <= '0';
word(i) <= input_bit;
i := i + 1;
if(i = 8) then
i := 0;
write_fifo <= '1';
end if;
end if;
end process gen_word;
A short "incomplete" bit of code above should help some