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Implementing a large size SRAM array in deep submicron CMOS technology

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Hi to all,
I am gonna design and simulate an SRAM array with size of 16kbit on 16nm PTM CMOS technology. However, this implementation becomes more complex and grueling through defining subcircuit in HSPICE. Now, what simulator can I employ to do this work?

Thanks a lot for helpful and hopeful comments
 

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