[SOLVED] Implementation of Radix 4 FFT in VHDL

[sougata_vlsi13]

I am using xilinx ISE 14.1 and i am getting a problem with the operand and multiple driver while implementing radix 4 FFT.
the problem is that
g2(0) <= add(s(1),mult(s(5),w(1)));
g2(0) <= add(s(1),mult(s(9),w(2)));
g2(0) <= add(s(1),mult(s(13),w(3)));

from g2 actually there are three expressions arising...i am not able to use any operand in between them like and/or/+ so that i can avoid writing three times g2(0) which is nothing but problem of multiple driver.
the error is HDL parser 808...and cannot be any operand in such context like that....so what should i do plz help
I am also attaching the snapshot of the prob.
Even though i have tried to convert those expressions in binary and then use the + operand in between but still the same problem persist....and even i tried with declaring function in the package with "and" but in either way also i was not able to solve the problem....so please help me

 

[TrickyDicky]

What is this "add" function?
where is it defined?
What type does it return?
What packages have you used in this project?

 

[sougata_vlsi13]

since i am dealing with the complex arithmetic...so for that purpose i use add function which is declared in the package...not only add i use sub and mult also which are used for subsequent operation.these functions are useful for floating point arithmetic.I have use only one packge which dealt with both real and imaginary part

 

[TrickyDicky]

you still didnt say what package it is. Is it from ieee.math_complex ? either way, for floating point you should not be using this - you should be using the floating point IP cores.

 

[sougata_vlsi13]

IEEE.MATH_REAL.ALL;this is the package

- - - Updated - - -

type complex is
record
r : real;
i : real;
end record;this is used for complex functions

 

[TrickyDicky]

yup, you cannot use that for synthesis. real types are not synthesisable or suitable for FPGA designs. They should only be used for testing purposes.

 

[sougata_vlsi13]

yes sir i agree with u... i am m using them only for testing purpose but how should i remove that error shown above in the ISE bcoz otherwise i had to forcefully drive that signal 3 times in which check syntax is ok but nthing but a problem of multiple driver.

 

[TrickyDicky]

Well, you cannot use or, because that would mean a logical or of the bits (and as it's real types, there are no bits). So you probably need a mux, which will need a select line to select which answer you want based on the criteria. But the big problem is - why are you even bothering with real types in ISE - it will not compile them.

 

[sougata_vlsi13]

sir i want to verify as what i was manually calculated in pen and paper...The code is working fine for me in case of radix 2 and split radix since i have to use signals which only drives single expression but here in this case it is driving three expression thts the issue...actually i want addition operation to be implemented there so is there any other way to recover the problem

 

[TrickyDicky]

like I said, have separate signals or make some kind of selection.