You have semicolons after all the if (xxxxx)
; which is wrong.
You are treating Verilog like a software language.
Here....
Code Verilog - [expand] |
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| if (count >= 1);
begin y0; end
if (count >=2);
begin y1; end
if (count >=3);
begin y2; end
if (count >=4);
begin y7; end
if (count ==5);
begin y10; end |
These statements are all done in parallel, and the only one that takes effect will be the count >= 1 as it's only not true if the count is 0. I'm pretty sure you were thinking each of the statements would occur one after the other, even though they all happen in parallel in a single clock cycle, hence the only one that is used is the first one since it is always true (disregarding the syntax problem with using a semicolon on the end of the if, truthfully I'm not even sure how the simulation should behave with that incorrect semicolon).
You also seem to think bare y0, y1, y2, etc are going to do anything, they won't they aren't assignments.
Basically your code is useless, incomplete, and not even functional. You need to find a better tutorial than the garbage you typically find on the internet. I suggest you buy an actual Verilog book or look for suggestions of good tutorials (which incidentally have been posted as links on edaboard). Besides that use Verilog 2001 module port declarations, they are both more concise and they will show you've made some effort to be "more" up to date.