Implementation of Counter in Verilog

[Spectre90]

Language: Verilog
Board: Xilinx Basys2

Hi

I am trying to make a counter that has a reset, clock (board's speed 50MHz), and a manual stop button inputs and outputs are 4-bits for a 7-segment-display.
However, i am trying to count from 1 to 9 (of course in a loop) and if i pressed the stop button, my output will be whatever the clock counted.
Also if reset is high, count goes back to 1.

i tried it but it doesnt work and i need help now.

Here is my code:

---

Code Verilog - [expand]
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module counting(
    input clk,stop,rst,
    output reg [3:0]b_out
    );
reg count = 1;
always@(posedge clk, posedge rst, posedge stop)begin
    if(rst)
         count = 1;
    else if (count > 9)
        count = 1;
    else if (stop)
        b_out = count;
    else
        count = count + 1;
end
endmodule

---

 

[mrflibble]

Quick notes:

- treat the reset button and stop button as regular boring inputs.
- add debouncing circuits for both the reset and stop input.
- only use clk in your sensitivity list of the always block. That way you'll get a nice synchronous circuit.
- inside the always block, where you now have rst and stop, you should then use the debounced version of those signals.

Hope that helps.

- - - Updated - - -

Oh yeah, and use non-blocking <= assignments instead of the blocking = kind you have now.

 

[ads-ee]

Your counter doesn't count from 1 through 9 it counts from 1 through 10.

I don't get how so many can't determine how to roll over a counter at the correct count value. else if (count > 9) means if count is 9: 9 > 9 is not true, so the next else if clause is executed, which means that count is going to be incremented again, therefore count == 10. Hello!?...so count is now 10!

 

[mrflibble]

Pssst, don't spoil the surprise on the other error. Let's leave that in as an easter egg for when a proper testbench is written.