Hi cwjcwjcwj,
For a DSP or a microcontroller implemetation of an algorithm written in "C for simulation purpose" you can use this code right away because C is a portable language. Which means that
idealy a C compiler for some Digital Signal Processing or a micrcontroller will accept the code and convert it to the corresponding machine language. But of course you will need to modify the code because compilers translate certain things their own way and if your chip is interfaced to other chips then you will need some more functions to manage this interface. And there are some implementation specific considerations like what to do if you're using a chip that doesn't support floating point arithmetic.Understanding the architecture of the DSP/microntroller you're dealing with will be the main task.
For FPGA-based implementations , you will need to imagine the algorithm as a logic circuit or at least as a block diagram of a digital system. But it doesn't mean you'll design this sytem from basic gates.You will write a Hardware Description Language
HDL code that descripes this digital system. The HDL will help you abstract certain elements of your design like for example addition,subtraction and logic comparison, usually you won't need to construct a FULL ADDER from scratch, by writing A+B the
synthesis tool will infer a full adder. But you will still need to deal with some lower level issues of your design like how to descripe your FSM if you need one , and how to optimize the device utilization , the clock ...etc Synthesis is conversion of a design written in HDL into a low-level implementation consisting of basic logic gates. Synthesis tools "read" your description and infer the hardware components. Understanding how the synthesis tool understands your description is important to optimize the code for best chip utilization.
Some tools like Xilinx System Generator automatically generate HDL code :
The Xilinx System Generator for DSP is a plug-in to Simulink that enables designers to develop high-performance DSP systems for Xilinx FPGAs. Designers can design and simulate a system using MATLAB, Simulink, and Xilinx library of bit/cycle-true models. The tool will then automatically generate synthesizable Hardware Description Language (HDL) code mapped to Xilinx pre-optimized algorithms. This HDL design can then be synthesized for implementation in Virtex-II Pro Platform FPGAs and Spartan-IIE FPGAs. As a result, designers can define an abstract representation of a system-level design and easily transform this single source code into a gate-level representation. Additionally, it provides automatic generation of a HDL testbench, which enables design verification upon implementation.
https://www.mathworks.com/products/connections/product_main.html?prod_id=304
The choice of implementation method depends on size, cost , power , performance and time to market constraints.
Edit:
I've just noticed the date of the main post. :|