Implementation of Algorithm in Hardware.

[cwjcwjcwj]

I am just curious how to implement algorithm into hardware. Let say, I have written a convolutional in C++ language for simulation purpose. Then, what should I do to implement in hardware?Is it using FPGA or VHDL?Any good informations about it? Thanks.

 

[Sal]

Hi

it depends on many things, lets say operation frequency, available power, costs and many other factors. It can be implemented in DSP as well

cheers

Sal

 

[boeysue]

mmm...
What a big vision on that problem!
The first one is which hardware do you want.
The sencond is which algorithm is your work.
.....
and etc.

 

[cwjcwjcwj]

Let say I am writting it in C++ language for simulation purpose. Then, which is the easiest way to implement in the hardward?ANd by the way, what method is the most common in industry nowadays.

 

[icyabhi]

Well it depends upon the h/w u r using...
along with ur h/w u'll get a specific tool or chk its manual for the tool used for transferring ur C++ or any code into h/w...

 

[faisalk]

There are two routes:

1) You can write your code in VHDL. Then simulate it in VHDL simulation tools like MODELSIM.Now you can synthesize it with ,say, VHDL synthesis and place and route tools like ALTERA's MAX+PLUS II. If you have any FPGA/CPLD development kit from ALTERA you can download your synthesised code and test in real hardware.

visit www.altera.com

2)You can write your code in C and simulate in your PC. Now if you have any DSP/microcontroller developemet kit and its associated cross-compiler (development system) you can download the .exe to the board and test it in real-hardware.

visit www.analog.com
Read this magazine :Embedded system design

 

[zhangpengyu]

data may be in float/fix point form.
then error must be considered.

 

[cmos babe]

Hi cwjcwjcwj,
For a DSP or a microcontroller implemetation of an algorithm written in "C for simulation purpose" you can use this code right away because C is a portable language. Which means that idealy a C compiler for some Digital Signal Processing or a micrcontroller will accept the code and convert it to the corresponding machine language. But of course you will need to modify the code because compilers translate certain things their own way and if your chip is interfaced to other chips then you will need some more functions to manage this interface. And there are some implementation specific considerations like what to do if you're using a chip that doesn't support floating point arithmetic.Understanding the architecture of the DSP/microntroller you're dealing with will be the main task.

For FPGA-based implementations , you will need to imagine the algorithm as a logic circuit or at least as a block diagram of a digital system. But it doesn't mean you'll design this sytem from basic gates.You will write a Hardware Description Language HDL code that descripes this digital system. The HDL will help you abstract certain elements of your design like for example addition,subtraction and logic comparison, usually you won't need to construct a FULL ADDER from scratch, by writing A+B the synthesis tool will infer a full adder. But you will still need to deal with some lower level issues of your design like how to descripe your FSM if you need one , and how to optimize the device utilization , the clock ...etc Synthesis is conversion of a design written in HDL into a low-level implementation consisting of basic logic gates. Synthesis tools "read" your description and infer the hardware components. Understanding how the synthesis tool understands your description is important to optimize the code for best chip utilization.

Some tools like Xilinx System Generator automatically generate HDL code :

The Xilinx System Generator for DSP is a plug-in to Simulink that enables designers to develop high-performance DSP systems for Xilinx FPGAs. Designers can design and simulate a system using MATLAB, Simulink, and Xilinx library of bit/cycle-true models. The tool will then automatically generate synthesizable Hardware Description Language (HDL) code mapped to Xilinx pre-optimized algorithms. This HDL design can then be synthesized for implementation in Virtex-II Pro Platform FPGAs and Spartan-IIE FPGAs. As a result, designers can define an abstract representation of a system-level design and easily transform this single source code into a gate-level representation. Additionally, it provides automatic generation of a HDL testbench, which enables design verification upon implementation.

https://www.mathworks.com/products/connections/product_main.html?prod_id=304

The choice of implementation method depends on size, cost , power , performance and time to market constraints.

Edit:

I've just noticed the date of the main post. :|