The errors mention RPM (Relative Place Macro or something like that). That means there are constraints on the placement of the I/O cells relative to other cells in the design. These are either from cores you created that have specific placement constraints or you ported some constraints from the old deign that don't apply correctly to the new design.
I would first try removing all constraints from the design and see if it's even possible to place and route the design in the part. Then start adding the constraints back in.
The errors you are seeing don't indicate there are too many I/O in the design, which would normally just report something like I/O can't be placed as there isn't an I/O available.