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Implementation error (ERROR: Place: 1500) on ISE 14.5

Cesar0182

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Greetings ... comment that a couple of days ago I have been adapting a project made in Vivado 2017.3 (Virtex-7) to ISE 14.5 because I need to work with a Virtex-5 device (xc5vlx155t-3ff1136), after making some changes, about All generate new IPs compatible with Virtex-5, I have successfully simulated and synthesized this new project. Now the problem that I am having is with the implementation since I get the following errors shown in the attached image.

error_implement.PNG

Someone who can help me with this problem please.
 

TrickyDicky

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This looks like your design has more IO than the device has pins available. To fix this you need to work out what you can disconnect from the IO and/or remove from the design.
 

ads-ee

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The errors mention RPM (Relative Place Macro or something like that). That means there are constraints on the placement of the I/O cells relative to other cells in the design. These are either from cores you created that have specific placement constraints or you ported some constraints from the old deign that don't apply correctly to the new design.

I would first try removing all constraints from the design and see if it's even possible to place and route the design in the part. Then start adding the constraints back in.

The errors you are seeing don't indicate there are too many I/O in the design, which would normally just report something like I/O can't be placed as there isn't an I/O available.
 

Cesar0182

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Thanks for your help TrickyDicky and ads-ee ... everything definitely indicates that the problem is because the constraints file (ucf) is missing. At this moment I need to generate one for this new design and the truth is I am something new in ISE, what information do I need to be able to create a UCF file? where can i find an example?
 

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