library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity cnt4od is
port
(
clk :in std_logic;
clr :in std_logic;
en :in std_logic;
cnt_o :out std_logic_vector(3 downto 0)
);
end;
architecture rtl of cnt4od is
signal cnt_i :unsigned(3 downto 0);
begin
process (clk,cnt_i)
begin
if rising_edge(clk) then
if clr = '1' then
cnt_i <= (others => '0');
elsif en = '1' then
cnt_i <= cnt_i + 1;
end if;
end if;
for i in 0 to 3 loop
if cnt_i(i) = '1' then
cnt_o(i) <= 'Z';
else
cnt_o(i) <= '0';
end if;
end loop;
end process;
end rtl;