Depending on what the performance requirements for the ADC are, the answer can be yes (mostly). The basic idea is that the FPGA generates a pulse width modulated output signal. This PWM signal is then low pass filtered to generate an analog voltage which is essentially the FPGA's estimate of the analog signal's voltage. External to the FPGA, in addition the low pass filter, you would need an analog comparator which compares the analog signal that you are trying to digitize with that of the filtered PWM signal just discussed. That comparator output is then a digital signal where a '1' indicates that the analog signal is higher than the FPGA's estimate; a '0' indicates that the analog signal is lower than the FPGA's estimate. If the FPGA's estimate is too high, then adjust it down; if it is too low, then adjust it up.
The limitations of the FPGA based ADC is primarily conversion speed. Since the FPGA is only receiving a 1 bit feedback on it's current estimate it can take a while for it to refine the estimate to match the analog voltage. Also, the PWM signal that needs to be filtered needs time to adjust to a new value. The more precision you desire, the longer the PWM stream needs to be. For example: for an 8 bit ADC you would need to output 256 clocks of '1' or '0' for the PWM output...this takes time. Lastly, if the analog voltage's range is just right, and the FPGA has differential inputs you might be able to use those differential input pins to implement the comparator instead of having it as an external device.
In short, it can be done, but the applications are for relatively low precision and slow A/D conversions.
Kevin Jennings