Hi,
If we should find the problem, then you need to give an error description first.
Klaus
Okay, I should have given at first ^_^
+) The first module receives data from users and send them to the second module through a single wire.
+) The second module receives data from the first module and processes the input data before showing results.
+) These numbers then will be added together in the calculation’s process in module 2.
- I put the same clock pulse for 74LS164 and 74LS166.
- At 74LS166, I put input data first by using Switch. 74LS166 transfer data (serial out) to B in 74LS164 (
(https://www.ti.com/lit/ds/symlink/sn54ls164-sp.pdf))
- In 74LS164, as A = VCC, whenever B is high, Q = 1.
For Example, if my input (D0->D7) = 00010001, then output at 74LS164 will be the same theoretically.
- These outputs go to 74LS83 (which is Full-Adder
https://www.futurlec.com/74LS/74LS83.shtml) and add together, the rest of the circuit is BCD to 7-segment decoder.
The problem is 74LS164 can't hold these outputs, continue "pushing" it and D0->D7 = 00000000.
- - - Updated - - -
How did you produce this circuit? Heave you written a test bench to test it
I just following requirements given in the problem, and my teacher suggestions too ^_^
+) The first module receives data from users and send them to the second module through a single wire. = 74LS166
+) The second module receives data from the first module and processes the input data before showing results. = 74LS164
- The received data in module 2 are the binary value of two 3-bits unsigned numbers. These numbers then will be added together in the calculation’s process in module 2.= 74LS83
The rest of the circuit is BCD to 7-segment decoder
I have written it on CircuitMaker2000 and the problem is 74LS164 can't hold the output and keep "pushing" it. Therefore, these outputs are 0 respectively.