impact config Spartan-II init chain error,cable III,

[stanleysan]

impact:1588

hi,all
i use impact 6.1i(43M) and a selfmade download parrallel cable connect to my xc2s200 evb board.

1 before,my download cable and impact can recognize xc9536xl on another board(not the same spartan board).
2 but now when i run init chain on this selfmade xc2s200 board,i get the follow info:

====
Cable connection established.
CB_PROGRESS_END - End Operation.
Elapsed time = 1 sec.
// *** BATCH CMD : Identify
PROGRESS_START - Starting Operation.
Identifying chain contents ....
INFO:iMPACT:1588 - '1':The part does not appear to be Xilinx Part.
'1': : Manufacturer's ID =Unknown , Version : 15
INFO:iMPACT:501 - '1': Added Device UNKNOWN successfully.
====
than i asssing a xc2s200.bsdl file this device and use a Get DeviceID comand, i get the following info:

Validating chain...
Boundary-scan chain validated successfully.
ERROR:iMPACT:583 - '1': The idcode read from the device does not match the idcode in the bsdl File.
INFO:iMPACT:1578 - '1': Device IDCODE : 00001111111111111111111111111111
INFO:iMPACT:1579 - '1': Expected IDCODE: 00000000011000011100000010010011Device #1 selected
================================
my question is :
1 is my download cable III(once successful with xc9536xl) suitable to xc2s200?
2 where my wrong?

thank you!

 

[eltonjohn]

spartan-ii bsdl file

MANY TIMES IN THIS FORUM WE HAVE DISCUSED HOW TERRIBLE IS THE CABLEIII DESIGN .. I ADVICE YOU TO BUY A CABLEIV ..OTHERWISE YOURS PROBLEMS ARE NOT OVER .. I HAVE THE REAL CABLEIII FROM XILINX AND IS TERRIBLE ..I REALLY DOESN'T WORK .... THE ONLY PROBLEM IS THAT CABLEIV IS $100 .. IT WOULD BE NICE TO CLONE IT !

 

[stanleysan]

impact device idcode

sorry to disturb you.but that error may not be cable fault....,if the jtag cable was wrong ,why i always get the some error idcode "0000111..." in my many tests, not some randm value?..
anybody can help me????please

 

[ilikebbs]

cable iii impact 501

maybe your power for fpga is not good.
you can use digital oscilloscope to monitor core volt and i/o volt.

 

[stanleysan]

impact 583 error

to i ilikebbs and others:
anther question:
is it mandatory to clock fpga's global clock input pin when jtag connecting?
i mean, when i use jtag connect board,i let the gck0(the only clock input in myboard) opend(not connect to osc).is it right?
thank you.