image processing using fpga.

[praveenvanaparthy]

hi ,
am trying to write code for image processing. for this first i just write data in one file to another.

my code is compiled successfully and simulated also. but doesn't create output file
am trying to write the data in input file into output file. but its not created any output file.
i made some changes also using commands like:
$writememb(".txt", w);
$fopenw();

but its not works properly.


my code is here:
module txtrd(in1,out1,clk);
input [3:0] in1;
reg [3:0] in ;
output out1;
reg[3:0]out1;
input clk;
reg [3:0] temp [0:15];
integer i,file;

initial
begin
$readmemb("input1.txt",temp);
end

always @(posedge (clk))
begin
for (i=0;i<=15;i=i+1)
begin
in = temp;
out1=in;

end

file=$fopen("output1.txt", out1);
for (i=0;i<=15;i=i+1)
begin
$display(file,"%b", out1);
end
end
endmodule

any changes is need for this. please tell me.


and another doubt is is there any possibility to read image directly into verilog, and is it
synthesizable and is it possible to dump on fpga.

please tell me ..

 

[syedshan]

Dear Praveen,

First of all the thing you are doing is not synthesizable.
You can read/write files only for simulation. This code cannot be dumped into the FPGA at all.

To read for the actual hardware of FPGA, you need to use some transmission protocol like USB, PCIe, UART etc.
Also from where are you getting your data, is it from computer, or from camera. This question is also answerable.

Also if you are looking for simulation only, I guess you did not close the file this might cause problem.
Use $fclose() to close you file. Use this link

any changes is need for this. please tell me.

Actually you have rewrite every thing with proper homework. It is good you tried though.
first google for some similar examples.
Use www.opencores.org or similar website to see the example projects.

Hope this helps

Bests,
Shan